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Linux/AM5728: A15 deactivation

Vincenzo Scianni54
Intellectual 310 points

Part Number: AM5728
Other Parts Discussed in Thread: CLOCKTREETOOL

Tool/software: Linux

Hello TI's experts.

I have some questions related to power consumption management coming from a specific need in my current project: I'm using A15 running under Linux mainly for web interface because for the rest of the functionalities I'm using DSP and Cortex M4. Because web connection is not used so often - less then 1% of the working time - and I have issues for power budget in POE mode I would like to ask:

1) From previous posts like this https://e2e.ti.com/support/arm/sitara_arm/f/791/t/551530 I know that I can switch off one of the two Cortex A15, but further : is it possible to freeze the other core waking up it only when there is Ethernet traffic ?

Reading AM572x TRM, in 4.3.7 a RETENTION low-power state supported by SR3-APG technology is presented and a FORCED_OFF + RETENTION state is described for both cores; further a FORCED_OFF only for MPU_C1 is indicated but it's not clear if I can use a combination of the two: my target is to put MPU_C1 in FORCED_OFF and MPU_C0 in FORCED_OFF + RETENTION to be waked up by Ethernet traffic. Is this possible ? Are there other ways to use only one A15 core running under Linux only when I have Ethernet traffic ?

2) There exists a tested code example implementing what I described ?

3) What are impacts on HLOS architecture using only mailboxes + shared memory but not IPC ? I suppose that if it's feasible to switch off the only core running Linux, then I'm completely free to use DSP and Cortex M4 without any other problem: is it true ? 

Thank you in advance for your support.

B.R.

Enzo.

  • 0 in reply to Vincenzo Scianni54
    TI__Mastermind 30786 points

    Vincenzo,

    Your use case is not one we typically support. It certainly may be possible, but not tested. So, we haven't tested the impact on HLOS like Linux. In our typical use cases, A15 running Linux is the master of the system and expected to be up and running. 

    Have you tried our Power Estimation Tool to confirm that shutting down the A15s is the best way for you to save power?

    http://www.ti.com/tool/POWEREST

    I am looking for software examples that might be useful to you, but I'm not sure I will find anything given the mismatch in use cases. I will reply back here if I find something that may be beneficial.

  • 0 in reply to RonB
    Intellectual 310 points
    Hello Ron.

    Thank you for your answer but let me ask a further clarification: is your typical use case contemplating only IPC ? I mean what you report is clear and coherent with a use case where I'm using IPC, but in case I'm using a simple mailboxes + shared memory architecture as suggested in this post : e2e.ti.com/.../604259 do I have the same constrains you are indicating ? Even in this case do I need to have A15 running Linux as master of the system ?

    Thank you in advance for your support.
    Best regards,
    Enzo
  • 0 in reply to Vincenzo Scianni54
    Intellectual 310 points

    Hello.

    No news about this topic ? And no answer to my observation ?

    Best Regards,

    Scianni Vincenzo

  • 0
    TI__Genius 13567 points

    Hi Vincenzo,

    I understand you want to power off the Cortex A15 cores when not in use. In Linux on the AM57xx this is done already. When one core is inactive, it is automatically clock gated. When both cores are inactive both are clock gated and power gated. There is only one power gate for both cores so you cannot power off one at a time. If you measure VDD_MPU power when Linux is idle, the power consumption you see will be due to the L2 cache which is "always on" separately from the power gate for the A15 cores.

    If you are aiming to reduce power, there are many modules in the SoC that are powered on by default in the Processor SDK. Disabling these modules can be done by marking them status="disabled" in the device tree. Here are modules I've been able to turn off without problem: BB2D, DCAN, DSS, HDMI, IVA, GPMC, GPU, PCIE, USB, VIP, and VPE. Most of those are by method of device tree, however some did require writing to PRCM registers and changing the state myself.

    Choosing what to turn off depends on your use case and the "Device Power-Management Layout" table in the AM572x TRM. Take the GPU voltage domain for example (VD_GPU). There is only one power domain in the voltage domain (PD_GPU). Inside the power domain is only one clock domain (CD_GPU). And in that clock domain is only one module, the GPU / SGX544. With the GPU disabled you can clock gate the CD_GPU. When a clock domain is gated, it still receives power and it consumes leakage current. Since all clock domains in PD_GPU turned off you can now power gate the PD_GPU. With PD_GPU power gated now leakage current is eliminated too. To try this out, go to the dra7.dtsi file, find the "gpu" node, and add status="disabled" to that node. Measure power on VDD_GPU before/after to see the effect.

    Further debug tips, use the command "omapconf ctt rd1" to dump a "rd1" file containing the clock states of modules in the SoC. This RD1 file can be opened in our CLOCKTREETOOL for you to evaluate which modules are currently receiving clocks. Essentially eliminate any unneeded modules, then any unneeded clock domains, then finally the power domains.

    Regards,

    Ahmad

  • 0 in reply to Ahmad_Rashed
    Intellectual 310 points

    Hello Ahmad.

    Thank you for your explanation and for your hints but there are two points that are not enough clear to me:

    1) You wrote: "When one core is inactive, it is automatically clock gated. When both cores are inactive both are clock gated and power gated. There is only one power gate for both cores so you cannot power off one at a time" but in 4.3.7.2 of TRM is written "FORCED_OFF mode applies only to MPU_C1": how is technically possible to switch off only one core if there is only one power gate for both cores ?

    2) You wrote: "...the power consumption you see will be due to the L2 cache which is "always on" separately from the power gate for the A15 cores." : are you referring to RETENTION low-power state ? Is RETENTION low power-state regarding only L1-cache or both ?

    Thank you and best regards,

    Scianni Vincenzo

  • 0 in reply to Vincenzo Scianni54
    TI__Genius 13567 points

    For Q1 and Q2,

    My last reply is only based on the "Device-Level Layout" table in section 3.4.1 of the TRM. It defines one power domain PD_MPU for both CPU0 and CPU1 and another power domain PD_MPUAON for the L2 cache, PLL, and INTC. There might be further power domains within PD_MPU as controlled by the MPU_PRCM_PRM_Cx registers in sections 4.4.6 and 4.4.8 but I'm not able to confirm if there is a physical power gate for each core or if these are just logical power states. In any case, Linux handles the power states for you.