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RTOS/AM5706: 2-channel Tamagawa encoder and EtherCAT

Sung-IL
Mastermind 31550 points

Part Number: AM5706
Other Parts Discussed in Thread: TIDEP-0101, AM5716

Tool/software: TI-RTOS

Dear Champs,

Is it possible to run 2ch Tamagawa Encoder and EtherCAT together on AM5706?

When I checked AM437x Tamagawa Encoder reference design(TIDEP-0101), it seemed only 1 pru core was used for tamagawa encoder. then, is it possible to run 2 tamagawa encoder to control 2 motors?

Thanks and Best Regards,

SI.

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Genius 10440 points
    SI,

    The Tamagawa Encoder example uses the PRU-ICSS UART along with a PRU GPIO pin to implement the interface. As you pointed out only one PRU core is needed to control this interface. However, there is only one PRU-ICSS UART available in the AM5706 (the Note under Figure 30-1 of the AM5706 TRM mentions that ICSS2 does not contain a UART peripheral).

    It may be possible to have the other PRU core control an SOC UART to implement the second Tamagawa interface, but there is no example provided for this and implementation would be up to the customer. Note that the data accesses to the SOC UART will have additional latency when compared to the local ICSS UART (from the PRU's perspective).

    Jason Reeder
  • 0 in reply to Jason Reeder
    TI__Mastermind 31550 points
    Hi jason,

    Thanks for this information.
    How about AM5716? I found there is 1 UART per each ICSS. If ICSS1 is used for Tamagawa Encoder and ICSS2 is used for EtherCAT, is it possible to use UART of ICSS2 for Tamagawa Encoder in ICSS1 with low latency?


    Thanks and Best Regards,
    SI.
  • 0 in reply to Sung-IL
    TI__Genius 10440 points

    Upon further review, we have data for these latencies posted here: http://processors.wiki.ti.com/index.php/AM57x_PRU_Read_Latencies

    PRU reading from its LOCAL ICSS UART: 13 cycles

    PRU reading from the OTHER ICSS UART: 40 cycles

    PRU reading from UART1-3: 60 cycles

    PRU reading from UART4-6: 40 cycles

    PRU reading from UART7-9: 38 cycles

    According to this data, on the AM5706 it would be nearly the same access latencies if the second PRU were accessing UART4-9 as compared to the AM5716 accessing the OTHER ICSS UART.

    Once again though, there is no example provided for this and the implementation would be up to the customer.

    Jason Reeder