Linux/AM3358: U-boot not detecting NAND

Hi Kemal,

I have created my own dts file and specified in u-boot config that this is the only file in the list. So as far as I am concerned, it is picked up and used. The mux.c file in u-boot/board/ti/am335x directory is not even compiled as part of the build. This is I believe due to the fact that use of device tree descriptors was specified in u-boot config as oppose to using hardcoded stuff. Doing anything with the mux.c file has absolutely no effect since it is not compiled/linked in.

Thanks,

Roman

The object file is not generated. As I said before, the file is not even compiled. And I can see why. The Makefile in board/ti/am335x states:

ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif

obj-y += board.o

So the mux.o is only included with CONFIG_SKIP_LOWLEVEL_INIT undefined.
Tracing it back, I find in include/configs/ti_am335x_common.h in lines 65-80:
.....
/*
* Since SPL did pll and ddr initialization for us,
* we don't need to do it twice.
*/
#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif

/*
* When building U-Boot such that there is no previous loader
* we need to call board_early_init_f. This is taken care of in
* s_init when we have SPL used.
*/
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_SPL)
#define CONFIG_BOARD_EARLY_INIT_F
#endif
....

That obviously means that I have to have SPL build or NOR boot enabled if the CONFIG_SKIP_LOWLEVEL_INIT is to be undefined. Neither of these are the case in our project. The SPL is completely disabled since we have our own first stage bootloader that is used to load u-boot. And the NOR boot is only optional.

But that's still somewhat beside the point. The u-boot should use the pinmux as defined in the device tree description. Not the hardcoded mux.c file.

Thanks,
Roman

Hi Steve,

We are not using SPL at all but do have proprietary first stage bootloader. I'll add the muxing there and try it.

Will keep you posted.

Thanx,

Roman

Si I have added the pin muxing in our first stage bootloader that loads and starts u-boot as follows:

unsigned int NANDPinMuxSetup(void)
{
/* GPMC_AD0 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(0)) =
( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_MMODE_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUDEN_SHIFT) |
( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUTYPESEL_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE_SHIFT);

/* GPMC_AD1 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(1)) =
( 0 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_MMODE_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUDEN_SHIFT)|
( 0 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUTYPESEL_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RXACTIVE_SHIFT) ;
/* GPMC_AD2 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(2)) =
( 0 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_MMODE_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUDEN_SHIFT)|
( 0 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUTYPESEL_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RXACTIVE_SHIFT) ;
/* GPMC_AD3 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(3)) =
( 0 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_MMODE_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUDEN_SHIFT)|
( 0 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUTYPESEL_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RXACTIVE_SHIFT) ;
/* GPMC_AD4 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(4)) =
( 0 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_MMODE_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUDEN_SHIFT)|
( 0 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUTYPESEL_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RXACTIVE_SHIFT) ;
/* GPMC_AD5 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(5)) =
( 0 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_MMODE_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUDEN_SHIFT)|
( 0 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUTYPESEL_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RXACTIVE_SHIFT) ;
/* GPMC_AD6 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(6)) =
( 0 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_MMODE_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUDEN_SHIFT) |
( 0 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUTYPESEL_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RXACTIVE_SHIFT) ;
/* GPMC_AD7 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(7)) =
( 0 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_MMODE_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUDEN_SHIFT) |
( 0 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUTYPESEL_SHIFT) |
( 1 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RXACTIVE_SHIFT) ;/* GPMC_WAIT0 */

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WAIT0) =
( 0 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_MMODE_SHIFT) |
( 1 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUDEN_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUTYPESEL_SHIFT)|
( 1 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_RXACTIVE_SHIFT);

/* GPMC_WPN */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WPN) =
( 7 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_MMODE_SHIFT) |
( 1 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUDEN_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUTYPESEL_SHIFT) |
( 1 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_RXACTIVE_SHIFT);

/* GPMC_CS0 */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CSN(0)) =
( 0 << CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_MMODE_SHIFT) |
( 1 << CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUDEN_SHIFT)|
( 0 << CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUTYPESEL_SHIFT)|
( 0 << CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_RXACTIVE_SHIFT);

/* GPMC_ALE */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_ADVN_ALE) =
( 0 << CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_MMODE_SHIFT) |
( 1 << CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUDEN_SHIFT) |
( 0 << CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUTYPESEL_SHIFT) |
( 0 << CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_RXACTIVE_SHIFT);

/* GPMC_BE0N_CLE */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_BE0N_CLE) =
( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_MMODE_SHIFT) |
( 1 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUDEN_SHIFT) |
( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUTYPESEL_SHIFT) |
( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_RXACTIVE_SHIFT);

/* GPMC_OEN_REN */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_OEN_REN) =
( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_MMODE_SHIFT) |
( 1 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUDEN_SHIFT) |
( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUTYPESEL_SHIFT) |
( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RXACTIVE_SHIFT);

/* GPMC_WEN */
HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WEN) =
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_MMODE_SHIFT) |
( 1 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUDEN_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUTYPESEL_SHIFT) |
( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RXACTIVE_SHIFT);

return TRUE;
}

That I hope is the proper match for the device tree version that works fine under Linux:

nandflash_pins_s0: nandflash_pins_s0 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */

AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */

AM33XX_IOPAD(0x874, PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};

However, even with the pin muxing set, the u-boot still stalls when trying to reset the NAND on first access to read IDs. Here is the u-boot log:

initcall: 8080eaeb (relocated to bff52aeb)
initcall: 8080eaeb (relocated to bff52aeb)
initcall: 8080eaeb (relocated to bff52aeb)
initcall: 8080eeb1 (relocated to bff52eb1)
initcall: 8080eaeb (relocated to bff52aeb)
initcall: 8080ef5d (relocated to bff52f5d)
NAND: uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
gpmc@50000000 - -1 -1
- not found
OF: ** translation for device gpmc@50000000 **
OF: bus is default (na=1, ns=1) on ocp
OF: translating address: 00000050
OF: parent bus is default (na=1, ns=1) on
OF: no ranges, 1:1 translation
OF: parent translation for: 00000000
OF: with offset: 1342177280
OF: one level translation: 00000050
OF: reached root node
fdtdec_get_int: gpmc,num-cs: 0x7 (7)
fdtdec_get_int: reg: 0x0 (0)
fdtdec_get_int: nand-bus-width: 0x8 (8)
fdtdec_lookup_phandle: ti,elm-id
nand: selected OMAP_ECC_BCH8_CODE_HW
RR elm_init
RR elm_init done
RR OMAP_ECC_BCH8_CODE_HW done
uclass_find_device_by_seq: 0 -1
uclass_find_device_by_seq: 0 0
timer@48040000 - -1 -1
timer@48042000 - -1 -1
timer@48044000 - -1 -1
timer@48046000 - -1 -1
timer@48048000 - -1 -1
timer@4804a000 - -1 -1
- not found
fdtdec_get_int: clock-frequency: 0x2dc6c0 (3000000)
OF: ** translation for device timer@48040000 **
OF: bus is default (na=1, ns=1) on ocp
OF: translating address: 00000448
OF: parent bus is default (na=1, ns=1) on
OF: no ranges, 1:1 translation
OF: parent translation for: 00000000
OF: with offset: 1208221696
OF: one level translation: 00000448
OF: reached root node

The output above ends with timer2 being initialized and used as timer for the NAND access delays as per code in drivers/mtd/nand/nand_base.c:

case NAND_CMD_RESET:
if (chip->dev_ready)
break;
udelay(chip->chip_delay);
chip->cmd_ctrl(mtd, NAND_CMD_STATUS, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
chip->cmd_ctrl(mtd,NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
/* EZ-NAND can take upto 250ms as per ONFi v4.0 */
nand_wait_status_ready(mtd, 250);
return;

The access times out after 400s (if not interrupted by watchdog reset). So there are obviously several issues here even with the pin muxing set in FSB/SPL. The chip access fails and the timing doesn't seem to be setup properly albeit configuration being the same as the am335x evm board. For reverence, here is the whole device tree used in both, u-boot and linux. And I stress again, it works perfectly fine in linux and we can read/write and access the nand partitions.

/*
* basic OBC DTS
*/

/dts-v1/;

#include "am33xx.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/* #include "am335x-bone-common.dtsi" */

/ {
model = "TI AM335x CSYS";
compatible = "ti,am335x-obc", "ti,am33xx";

memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 256 MB */
};

chosen {
stdout-path = &uart0;
};

};

&rtc {
status = "disabled";
ti,hwmods = "disabled";
};

&am33xx_pinmux {
pinctrl-names = "default";
pinctrl-0 = <&clkout2_pin>;

i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,pins = <
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
>;
};

i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
>;
};

uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
>;
};

uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
>;
};

clkout2_pin: pinmux_clkout2_pin {
pinctrl-single,pins = <
AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
>;
};

nandflash_pins_s0: nandflash_pins_s0 {
pinctrl-single,pins = <
AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */

AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */

AM33XX_IOPAD(0x874, PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
>;
};

};

&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;

status = "okay";
};

&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;

status = "okay";
};

&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;

status = "okay";
clock-frequency = <100000>;
};

&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;

status = "okay";
clock-frequency = <100000>;

};

&elm {
status = "okay";
};

&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nandflash_pins_s0>;
ranges = <0 0 0x10000000 0x10000000>; /* CS0: 16MB for NAND */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 0x1000000>; /* CS0, offset 0, size 16MB or the TI code in omap-gpmc.c will screw up! */
ti,nand-ecc-opt = "bch8";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,time-para-granularity = <1>;
gpmc,device-width = <1>;
gpmc,burst-width = <0>;
gpmc,burst-wrap = <0>;
gpmc,sync-clk-ps = <40000>; /* converted to ps */
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <300>; /* values are 10x higher (from standalone where it is in ticks) */
gpmc,cs-wr-off-ns = <100>; /* as they are later divided using clock rate formula */
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <100>;
gpmc,adv-wr-off-ns = <100>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <50>;
gpmc,oe-on-ns = <0>;
gpmc,oe-off-ns = <100>;
gpmc,access-ns = <110>;
gpmc,rd-cycle-ns = <300>;
gpmc,wr-cycle-ns = <100>;
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-access-ns = <0>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "boot";
reg = <0x00000000 0x08000000>;
};
partition@1 {
label = "root";
reg = <0x08000000 0x78000000>;
};
};
};

&usb {
status = "okay";
};

&usb_ctrl_mod {
status = "okay";
};

&usb0_phy {
status = "okay";
};

&usb1_phy {
status = "okay";
};

&usb0 {
status = "okay";
};

&usb0 {
status = "okay";
dr_mode = "host";
};

&usb1 {
status = "okay";
dr_mode = "host";
};

&cppi41dma {
status = "okay";
};