Linux/AM5718: VOUT1 sync jitter

Hi,

There is silicon errata i886 which has known issue with DSS's video PLL causing jitter, but some DSS video PLL dividers reduce the jitter. The workaround for i886 errata is available in Processor SDK 4.2 (kernel version 4.9.59). Here's the commit id and details -

commit 864eb8ae83e8a7c98828a9b7978a053deee4a040
Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
Date: Tue Jan 5 11:43:13 2016 +0200

drm/omap: work-around for errata i886

DRA7 errata i886 (FPDLink PLL Unlocks With Certain SoC PLL M/N Values)
says that FPDLink is sensitive to jitter on the vout clock, and that low
PLL M and N values result in more jitter than high M and N values.

This patch implements a workaround for the problem by changing the PLL
setup to search for clocks starting from high M and N values, instead of
low values. This should not cause any functional change, and only
reduces the jitter.

You can try this workaround. If this doesn't work, then you will need to check io delays and other hardware related fixes.

Regards,
Manisha

Thanks for reply.

I am using ti-processor-sdk-linux-am57xx-evm-04.01.00.06.The patch have been applied in the sdk.

.

commit 864eb8ae83e8a7c98828a9b7978a053deee4a040
Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
Date:   Tue Jan 5 11:43:13 2016 +0200

    drm/omap: work-around for errata i886

commit 864eb8ae83e8a7c98828a9b7978a053deee4a040
Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
Date: Tue Jan 5 11:43:13 2016 +0200

drm/omap: work-around for errata i886

DRA7 errata i886 (FPDLink PLL Unlocks With Certain SoC PLL M/N Values)
says that FPDLink is sensitive to jitter on the vout clock, and that low
PLL M and N values result in more jitter than high M and N values.

This patch implements a workaround for the problem by changing the PLL
setup to search for clocks starting from high M and N values, instead of
low values. This should not cause any functional change, and only
reduces the jitter.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

diff --git a/drivers/gpu/drm/omapdrm/dss/pll.c b/drivers/gpu/drm/omapdrm/dss/pll.c
index 0a76c89..65c478d 100644
--- a/drivers/gpu/drm/omapdrm/dss/pll.c
+++ b/drivers/gpu/drm/omapdrm/dss/pll.c
@@ -231,7 +231,7 @@ bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,

pll_max = pll_max ? pll_max : ULONG_MAX;

- for (n = n_start; n <= n_stop; ++n) {
+ for (n = n_stop; n >= n_start; --n) {
fint = clkin / n;

m_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2),
@@ -240,7 +240,7 @@ bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
(unsigned)(pll_hw_max / fint / 2),
hw->m_max);

- for (m = m_start; m <= m_stop; ++m) {
+ for (m = m_stop; m >= m_start; --m) {
clkdco = 2 * m * fint;

if (func(n, m, fint, clkdco, data))

--------------------------------------------------------------------------------------------------------------------------------------------
But I roll back the patch,the image looks like better than before.Why?

diff --git a/drivers/gpu/drm/omapdrm/dss/pll.c b/drivers/gpu/drm/omapdrm/dss/pll.c
index 65c478d..1d45f44 100644
--- a/drivers/gpu/drm/omapdrm/dss/pll.c
+++ b/drivers/gpu/drm/omapdrm/dss/pll.c
@@ -231,7 +231,8 @@ bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,

pll_max = pll_max ? pll_max : ULONG_MAX;

- for (n = n_stop; n >= n_start; --n) {
+// for (n = n_stop; n >= n_start; --n) {
+ for (n = n_start; n <= n_stop; ++n) {
fint = clkin / n;

m_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2),
@@ -240,7 +241,8 @@ bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
(unsigned)(pll_hw_max / fint / 2),
hw->m_max);

- for (m = m_stop; m >= m_start; --m) {
+// for (m = m_stop; m >= m_start; --m) {
+ for (m = m_start; m <= m_stop; ++m) {
clkdco = 2 * m * fint;

if (func(n, m, fint, clkdco, data))

Can you capture the PLL configuration with and without the errata workaround - (maybe printing the PLL_CONFIGURATIONx registers in dss_pll_write_config_type_a)?

You can also try to use HDMI PLL. It doesn't have the jitter issue as VOUT clocks. .Attached hack patch to make AM5 EVM use it. HDMI output must be disabled (You can do so in the dts), and the dpi.c driver needs to be changed to use HDMI PLL for the DPI output.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0001_2D00_hack_2D00_to_2D00_disable_2D00_hdmi_2D00_and_2D00_use_2D00_HDMI_2D00_PLL_2D00_for_2D00_VOUT1.patch

Thanks for reply.

I set the pixel clk to 80Mhz from dts.other parameters change to 720p.

clock-frequency = <80000000>;

Default in sdk 4.1 with the errata workaround,dump registers

DISPC_DIVISOR1  0x00010002
PLL_CONFIGURATION1    0x014DC04E

2*20*(1760)/40/12 = 160Mhz

160/2=80Mhz

but the image is bad.

without the workaround,and I improve the limite of the video pll input from software.dump registers

PLL_CONFIGURATION1    0x00000400
DISPC_DIVISOR1  0x00010001

2*20*(2)/1=80Mhz

80/1=80Mhz

The image on the screen is good,I can accept it.

So, It is opposite from errata .

And I will try the hdmi pll.