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McBSP Internal Fsync generation

K Md Feroz Irfan
Expert 7225 points

Hello Champs!

 

Our customer has used 5502 McBSP port as a slave mode i.e. Clock signal and Frame Sync signal is provided externally.

 

Now, in new design we want to reduce the cost of WAN PLL by removing frame sync generation by PLL. For that we have to generate frame sync pulse by internal clock generator of McBSP port. So,

 

1. Can we generate only frame sync pulse by internal generator of McBSP port while Clock signal is fed externally on RCLK and TCLK pin?

    a. if yes, then is there any other impact on DMA ?

    b. if no, then is it compulsory that, Clock will be also generated internally for working McBSP as master mode?

 

Awarding your response

 

Best Regards,

Feroz

  • 0
    TI__Guru*** 125430 points

    To make sure I'm clear, you want to:

    1. Provide clocks externally on CLKX/CLKR of the McBSP.
    2. Generate a frame sync and output on FSX/FSR.

    To do this I recommend that you configure the sample rate generator such that it is being clocked by CLKX/CLKR.  See Table 3-2 "Choosing an Input Clock for the Sample Rate Generator With the SCLKME and CLKSM Bits" in the McBSP guide for proper register settings.  Then you can configure the sample rate generator to output a frame sync at the desired frequency.  In the PCR register you configure which pins are inputs and which are outputs.

    It's important to note that you should NOT derive the frame sync from a different clock.  In other words, you really NEED to configure the sample rate generator to be clocked from CLKX/CLKR and not simply generate your own clock by dividing down the CPU, etc.  Otherwise your clocks will have slight skew and will ultimately cause extra clocks, etc.