RTOS/TMS320C6678: PCIe LLD driver sample

Andrew Dunlap

Part Number: TMS320C6678

Tool/software: TI-RTOS

I have a DSP C6678 that I need to configure as the root complex (RC) and it will connect to an FPGA configured as a single endpoint (EP). I only have one lane and it will be configured for Gen 1 (2.5 Ghz). The DSP (RC) will always initiate transfer for read/writes to the FPGA (EP). The FPGA will never initiate a read/write request.

I am trying to get the sample program provided with the pdk_c667x_2_0_0 for the c6678 to work. I have compiled the sample code that uses the driver located in the pdk at ti/drv/pcie/example/sample/src/pcie_sample.c. I have linked to the driver in ti/drv/pcie/lib/c6678/c66/ti.drv.pcie.c6678.ae66. In the main function, pcie(), the code gets to the function pcieWaitLinkUp(), where it polls forever looking for the LTSSM state to reach LO (0x11). This can be seen in DEBUG0 (0x2180 1728) LTSSM_STATE field.

The main problem is the PCIe LLD API calls for Pcie_readRegs and Pcie_writeRegs do not seem to be working. Using the sample when I try to disable link training in the function call pcieLtssmCtrl(), the function succeeds with a return value of pcie_RET_OK, but I can't disable or enable the link training. I'm looking at 0x21800004 for the LTSSM_EN bit to change.

Have I configured something wrong with the sample project for the C6678?

over 7 years ago

0 Yordan Kovachev over 7 years ago

TI__Guru**** 161600 points

Hi,

The RTOS team have been notified. They will post their feedback directly here.

Share which TI RTOS version are you using.

Best Regards,
Yordan

0 Andrew Dunlap over 7 years ago in reply to Yordan Kovachev

Prodigy 90 points

Hi Yordan, I have the following configuration.

Code Composer Studio 6.1.2

Sys/Bios 6.45.01.29

XDCTools 3.32.00.06

Compiler 8.1.2

Pdk_c667x_2_0_0

0 lding over 7 years ago in reply to Andrew Dunlap

TI__Guru* 95265 points

Hi,

I don't have that version of PDK but I have the latest Processor SDK RTOS 4.2, I looked at code and it looked OK. The Pcie_readRegs and Pcie_writeRegs are common APIs we used for all the registers. For the particular pcieLtssmCtrl(), the used register structure is deviceCmd.

I tried to call enable and disable ltssm with this API and checked at 0x2180_0004 bit 0, there is no issue. Also, we have system test of PCIE for every release, and the PCIE link always came up, which meant API worked. I am not sure why you see the problem. If you still see the problem, you may directly write that register bypassing the API.

Regards, Eric

0 Andrew Dunlap over 7 years ago in reply to lding

Prodigy 90 points

I agree the api works, but I'm not sure why I don't see any changes to any registers when using Pcie_writeRegs. I never get a stable link state using the API. I added a function at the bottom of the sample called TestOutboundAddressTranslation(), where I read and write the registers directly. Using this method I can modify the registers and get a stable link state. I'm attaching my code for reference.pciesample-3.zip

0 lding over 7 years ago in reply to Andrew Dunlap

TI__Guru* 95265 points

Hi,

"why I don't see any changes to any registers when using Pcie_writeRegs." =====> there are many registers were written by this API before enabling the link training, like configure the inbound, outbound translation, enable error reporting. ... Are you saying all of them are not reflected on the register view after each API write?

Note, you don't need to connect to an PCIE EP for any such test. After you enable the PCIE power domain you should be able to do this. Is this C6678 EVM used in the testing?

Regards, Eric

0 Andrew Dunlap over 7 years ago in reply to lding

Prodigy 90 points

Hi Eric, that is correct. all of them are not reflected on the register view after each API write. This was tested on the C6678 EVM and my target hardware, with the same results. You can see in the screenshot that I'm trying to set the obSize = pcie_OB_SIZE_8MB, which means the register at address 0x2180 0030 should be set to the value 0x3. It remains zero, and the retVal = pcie_RET_OK. I am sure I have something configured incorrectly, but I can't seem to find out what it is.

0 lding over 7 years ago in reply to Andrew Dunlap

TI__Guru* 95265 points

Hi,

I compiled the PCIE test sample and tried on my 6678 EVM, I attached here please have a try. Note I commented out the below for testing purpose (after EVM PCIE is powered on, the API should be able to program the PCIE registers)

while (!lock)

{

CSL_BootCfgGetPCIEPLLLock(&lock);

}

[C66xx_0] **********************************************

* PCIe Test Start *

* RC mode *

**********************************************

Version #: 0x02020008; string PCIE LLD Revision: 02.02.00.08:Mar 29 2017:17:25:23

Power domain is already enabled. You probably re-ran without device reset (which is OK)

PCIe Power Up.

**********************************************

* PCIe Test Start *

* RC mode *

**********************************************

Version #: 0x02020008; string PCIE LLD Revision: 02.02.00.08:Mar 29 2017:17:25:23

Power domain is already enabled. You probably re-ran without device reset (which is OK)

PCIe Power Up.

PLL configured.

Successfully configured Inbound Translation!

Successfully configured Outbound Translation!

Configure PHY Loopback...

Starting link training...

My PDK is C667x 2.0.5, neither your version nor the latest. The C66x PDK is in maintenance mode, no PCIE driver changes so I hope the different versions doesn't matter. Please try my example to see if you have registers reflected before we determine the next steps.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/PCIE_5F00_evmc6678_5F00_wSoCFile_5F00_C66BiosExampleProject.out

Regards, Eric

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RTOS/TMS320C6678: PCIe LLD driver sample