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TDA2xx IPU subsystem

Guy Mardiks
Genius 4135 points

Hello,

On the TDA2xx TRM there are two IPU subsystems. according to the TRM IPU1 - is for general purpose while IPU2 is for IVA-HD.

On the L3 Main Map IPU2 is shown to be mapped to 0x55000000 - 0x5508xxxx while IPU1 to 0x5800xxxx - 0x5888xxxx.

could there be a mistake and the addresses marked for IPU2 are for IPU1 and vice-versa?

(on the SBL it initializes the CTRL_CORE_CORTEX_M4_MMUADDRTRANSLTR with 0x55020. I would expect SBL to initialize the general IPU (IPU1) but the address belongs according to TRM to IPU2 RAM)

also can you please provide explanation as to what is the purpose of the CTRL_CORE_CORTEX_M4_MMUADDRLOGICTR register - no description is provided  on the TRM .

Thanks

  • 0
    TI__Guru 55685 points
    Hi Guy,

    Please find below answers to your questions:
    1. There is no restriction like IPU1 - is for general purpose while IPU2 is for IVA-HD. This was applicable to older platforms.
    Can you please specify which version and chapter of TRM has this information so that I can get TRM corrected.
    2. CTRL_CORE_CORTEX_M4_MMUADDRTRANSLTR is mapped to IPU's private address. If you see the TRM chapter "Dual Cortex-M4 IPU Subsystem Register Manual" you will see that there are two addresses being talked about: IPU's private address and L3 address. IPU2 is at 0x55000000 - 0x5508xxxx in L3 map whereas on IPU map both are at address 0x5508 0000.
    3. CTRL_CORE_CORTEX_M4_MMUADDRLOGICTR is used at the time of IPU wake up to configure boot translation page of IPU to IPU RAM. This is the virtual address register. You can refer to SBLLibIPU1SubsystemReset() API to see its use.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Genius 4135 points
    I am looking at the latest TRM i have found:

    Literature Number: SPRUI29D
    November 2015–Revised April 2017

    The function for IPU1 is and same as for IPU2 - so since it refers to internal IPU address and the internal mapping is the same both functions are the same?

    under the control module i see only one set of registers CTRL_CORE_CORTEX_M4_MMUADDRTRANSLTR , CTRL_CORE_CORTEX_M4_MMUADDRLOGICTR - no mention of to which IPU it applies and where is the set for the second one? both functions (IPU1 and IPU2 configures the same registers)?

    I am still unclear about what does the CTRL_CORE_CORTEX_M4_MMUADDRLOGICTR register does (again no description and it is being written to zero in the function which is also its reset value ).

    Thanks,
    Guy.
  • 0 in reply to Guy Mardiks
    TI__Genius 14190 points

    Hello Guy, 

    as for the TRM question, indeed I checked with the team and in the upcoming releases this will be fixed, i.e. both IPUs are for general use.

    As for the register question, let me check with the control module experts and will get back to you soon.

    Thanks,

    Alex

  • 0 in reply to Guy Mardiks
    TI__Guru 55685 points
    Hi Guy,

    Let's discuss this and other questions/issues in tomorrow's call.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    TI__Guru 55685 points
    Hi,

    This issue was resolved during the call.
    1. 0x5502_0000 is IPU's view and will be same for both IPUs. At L3 level we have different views.
    2. To start M4 0x0 needs to be mapped from IPU's view. CTRL_CORE_CORTEX_M4_MMUADDRTRANSLTR is physical address and other is logical address. There is only set for both IPUs.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Genius 4135 points
    There still seem to be some confusion of TRM versus the actual usage on the SBL example.
    TRM mentions that the 0 small page VIRTUAL/LOGICAL address initialized after reset with the value of the MMUADDRTRANSLTR while the physical address of that page is initialized after reset with a fixed value of 0x5502, no mention of any usage of the MMUADDRLOGICTR register at all . on SBL example the MMUADDRTRANSLTR is set with the 0x5502 - but this is the physical address we want.

    Guy
  • 0 in reply to Guy Mardiks
    TI__Guru 55685 points
    Hi Guy,

    As we discussed in yesterday's call this seems to be an error in TRM. I have already filed a TRM bug to get this rectified.

    Regards,
    Rishabh