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TMS320C6657: Cache, MSMC and so on

Part Number: TMS320C6657

Hello Forum, 

i have some difficulties in getting correct data in my application.

In my app Core 1 only handels uPP Datatransfers. The Buffers are globally defined in the following way:

#pragma DATA_SECTION(rcvBuffer_0,".far:uPPrcv_0");
#pragma DATA_ALIGN(rcvBuffer_0,CACHE_L2_LINESIZE);
int16_t rcvBuffer_0[DATASIZE];

The Sections in the app.cfg are defined :

Program.sectMap[".far:uPPrcv_0"]				 = "MSMCSRAM";

On Core 0 i have the buffers 

extern far int16_t rcvBuffer_0[DATASIZE];

Core 0 also transmits these buffers via Ethernet to a PC (UDP).

to do this i have another buffer for the header, checksums, data and so on.

at least this buffer is copied to the descriptor as in the Benchmarc example given.

Q1: do i have to use the global adresses for upp-DMA also on Core 0 for MSMC-Ram ?

Q2: on Core_1: before the uppDescriptor is written i invalidate L2 and L1D, when the data transfer is finished i do a CacheWbL2 and L1, correct?

Q3: on Core_0: before the data is copied (with memcpy() always) i have to CacheWbL2 and L1, right?

Q4: on Core_0: before the Eth-descriptor is send, i have to CacheWbL2 and L1, right?

In Sum i have 3 Buffers. Core_1 writes to Buf0, in that time Core_0 reads from Buf2, and so on.

Behavior is that the data freezes after some time, but not periodically.

Many thanks for any answers.

Best Regards

Martin