MAR settings for swapping between cache/SRAM L1D on DM6435

MattLipsey said:

I use the edma to page memory in & out of SRAM for my large blocks, but do I need to worry about potential accesses to memory ranges that are cache enabled when my cache is set to size 0? 

I don't believe there is any issue with accessing locations with the MAR set to cacheable while you have a L1D cache size of 0, apart from the accesses being inefficient due to the lack of cache. As long as you are keeping cache coherency in mind when performing the DMA transfers and enabling and disabling L1D everything should be fine, are you running into some sort of data corruption issue?

No, I went through the steps of changing from all sram to cache only to find no improvement in the cache using section of my processing.  I then tracked down the silly mistake of not setting the MAR bits for the memory range I care about.  I was just wondering if I could set these bits at initialization or if I had to write functions to turn them on/off around the sections of interest. 

MattLipsey said:

I was just wondering if I could set these bits at initialization or if I had to write functions to turn them on/off around the sections of interest. 

You certainly can, the only reason you would turn the MAR bits back off would be if you wanted to avoid having to perform cache coherency operations for the memory segment in question, or if you wanted to leave the cache space open for some other section to have more exclusive cache space.