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Codec operation on DM6446

Sid
Genius 4530 points

Other Parts Discussed in Thread: TLV320AIC33

Hi,

I am working on DM6446 DVEVM board.

In the guidelines document, I found the following statements

The McBSP’s DX pin on the DM644x can be configured to operate as a SPDIF
transmitter. The DM644x EVM supports a single SPDIF output with both analog and
optical interfaces. The analog SPDIF output pin is routed to a level translator then to a
driver and filter circuit before being output on J13. The same level translator is used for
another driver which then drives the optical transmitter U65. When the SPDIF interface
is enabled the TLV320AIC33 codec is disabled.

Presently, my SPDIF interface is enabled, but I cant find any guidelines to disable it and thereby enable my codec.

Can anyone guide me in this case?

Thanks and Regards,

Sidharth

  • 0
    TI__Mastermind 41665 points

    Looking at the schematics from that technical reference it seems that the codec is gated by the McBSP_EN signal on the daughtercard, if it is pulled high the on board codec will be disconnected by a buffer (U53), so if McBSP_EN is left low (or disconnected due to the on board pull down resistor) the codec should be enabled.

  • 0
    Genius 4530 points

    Hi Bernie,

    Thanks for your reply.

    Actually, under the present circumstances, the data on the DX line used to run the codec is getting transferred automatically to SPDIF OUT optical interface.

    This means that McBSP_En has a default state of  1 (high) without connecting any daughter card. Does this mean that if I give it an external signal and assign 0 to it, and then disconnect the signal, it will assume a permanent value of 0 till I change its value? And is there any specific daughter card to be used for this purpose?Or I can use an external source?

    Thanks and Regards,

    Sidharth

     

  • 0
    Prodigy 20 points

    DM6446 daughter board may be required.

  • 0
    Intellectual 400 points

    Hi Sid,

    I am working on DM6446 EVM's SPDIF module. The EVM version that is being used by me is RevF

    From the schematic I see that SPDIF and CODEC are not mutually exclusive, but TRM states "When the SPDIF interface is enabled, the TLV320AIC33 codec is disabled."

    If I go by the statement in TRM, the audio clock must be supplied by SOC. The default input clock rate for ASP is 99000000MHz, which is too large(even after setting maximum divisor value in ASP) for setting maximum supported audio bit rate(96KHz), i.e in order to operate SPDIF, clock must be supplied by CODEC.

    Please confirm on my understanding

    Thank you