[Jacinto6 evm board, model: TI DRA742] Inner / Outer Shareability domains implementation

Hi Marine,

It seems that the documentation you are referring to is only applicable to A15 and not M4, so I want to confirm.
Can you share the link of ARM documentation.

Regards,
Rishabh

Hi Rishabh,

Thank you for your reply.

Indeed I was referring to the ARM Architecture Reference Manual for ARMv7-a and ARMv7-r (Section A3.5.2 Summary of ARMv7 memory attributes, page 127 ). Following is the link to the document: static.docs.arm.com/.../DDI0406C_C_arm_architecture_reference_manual.pdf

So I think you are right, it does not apply to M4. As explained in ARM documentation, Shareability domains are implementation defined, that's why I also have been through TI DRA74xx documentation. However I didn't find any information about this matter. Do you have an idea where I could find such information?


Regards,
Marine

Hi Marine,

Can you please look at below links:
infocenter.arm.com/.../index.jsp
community.arm.com/.../the-exact-definition-of-outer-and-inner-in-armv7
If you refer to the diagram given in these links and MPU Subsystem Overview diagram from the TRM you will be able to conclude that both L1 (I & D) and L2 caches are in the inner shareable domain.
Also TI DRA74xx implements LPAE and hence device memory is outer shareable.

Regards,
Rishabh

Hi Rishabh,

Thanks for the links.
So I looked at these documents. The diagrams describe examples of possible implementations.

Device memory is indeed required to be outer shareable, as specified in ARM documentation. However, I am missing the point where M4 cluster and A15 cluster are mandatory to be in the same inner shareable domain.
I guess these clusters could also be in different inner shareable domains, as they must be able to run different operating systems. This architecture is for example represented in the section "Figure 13.4. Inner and outer shareable domains" of infocenter.arm.com/.../index.jsp.

Could you please clarify the role and the shareability domain implementation of the M4 cluster?

Regards,
Marine

Hi Marine,

I am not able to understand the problem. This documentation is not applicable to M4 as I specified earlier.
Hence M4 doesn't have the concept of shareable domains.

Regards,
Rishabh

Hi Rishabh,

According to DRA74x documentation, the M4 clusters (IPUs) own 2 levels of caches and has access to L3 main memory. That is why I conclude there is still a need of coherency for the data which is shared by IPUs and other masters (GPU, MPU, ...) in the system.

What I understood is that Shareability domains are defined globally for a system, and that means all units need to be assigned to one inner/outer/system shareable domain. These domains represent different granularities to apply the minimum of hardware coherency to guarantee the global coherency of the system.

" M4 doesn't have the concept of shareable domains": So if M4 doesn't support Shareability, I guess IPUs are also part of the outer shareable domain, and that internal coherency must be handled in software (running on the M4s cores).

Could you please confirm this reasoning or tell me where I am wrong?

Regards,
Marine

Hi Marine,

IPU has only one cache i.e. Unicache. There are two levels of MMU.
Can you tell me what section of TRM says that there are two levels of cache.

Regards,
Rishabh

Hi Rishabh,

You are right there is only one level of cache. I got confused with MMU and cache. I was refering to the section "7.1 Dual Cortex-M4 IPU Subsystem Overview".
But the conclusion is still the same to me, we need to maintain coherency for the data which is shared by IPUs and other masters (GPU, MPU, ...) in the system.

Regards,
Marine

Hi Rishabh,

Thanks a lot for your explanation. Coherency implementation in this particular case is now much clearer for me.

Regards,
Marine