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NAND ECC generation

Hello, I have a board with a DRA457 that has a Micron MT29F4G08ABA (4Gbit).

My question is what algorithm (and bit correction) does the hardware ECC use to generate the OBB ECC data?

I can see at OOB/Spare offset 0x02 there are 10 bytes for the page of 2048 bytes.

Thank you.

  • Ryan,

    CRC 32 polynomial is used for CRC calculation. It is listed below for reference (the xN notation means to the power of N):
    ×2 + ×26 + ×23 + ×22 + ×16 + ×12 + ×11 + ×10 + ×8 +×7 + ×5 + ×4 + ×2 + × + 1

    Regards,
    Kyle