Part Number: OMAP-L138
Other Parts Discussed in Thread: OMAPL138
A test in DLB mode: Q channel transmit, I channel receive.
#1. Q channel DMA transmit 96byte 0x17, I channel DMA configured to receive 72byte. test result I channel received 72byte 0x17 as expected.
#2. Q channel DMA transmit 96byte 0x18 again, I channel DMA configure to receive 72byte. test result I channel received 72byte 0x18.
Question: why the #2 received data is not 24byte(96-72) 0x17 of #1, plus 48byte(72-24) 0x18 of second transmit? where is the 24byte 0x17 in FIFO?
Further debug found.
If configure #2 receive DMA when ACT=1(active), #2 receive 24byte 0x17 + 48byte 0x18.
If configure #1 receive DMA when ACT=0(inactive), #2 receive 72byte 0x18, 0x17 in FIFO was cleared.
As there is no detail description about uPP FIFO working mechanism, is it explainable?
