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RTOS/AM5728: SPI CS toggle between frames

Pratik Parvati
Prodigy 150 points

Part Number: AM5728

Tool/software: TI-RTOS

Hi Support team,

                            I'm writing a driver for a device sitting over SPI on AM5728. I'm writing the driver in Sys/BIOS. I've configured the SPI controller for single channel operation and data size of 32 bits. Also the  interrupts are enabled as well. The device expects CS to be active low and toggle from high to low after each word transfer.  Thus if I'm doing  an SPI write of 2 words (each word is 32 bit), the device expects CS to go high after each word transfer and come back to active low to start the next transfer...
 
             However when I probe the CS signal through an oscilloscope, I see that the CS remains active low till on the modes are transferred. My question is whether there is a way to ensure that CS line toggles from high to active low after every word transfer before the next word starts? The data sheet says that for single channel transfer, the CS will always remain active till all the words are transferred. Is there a way to change this default behavior. I want CS to toggle from high to low after every word transfer. Is there any register programming that I should be doing?
thanks
Pratik

        

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0
    TI__Guru** 116870 points
    Pratik,

    Sorry for the delayed response here. We don`t support custom driver development here so beyond providing device level guidance, we will not be able to extend support unless you are using TI Processor SDK RTOS driver SPI driver.

    Are you putting both the words in the TXFIFO and then waiting for the transaction to complete? I recommend that you look at TI MCSPI driver implementation at MCSPI_transmitData_v1 in the file pdk_am57xx_1_0_9\packages\ti\drv\spi\src\v1\SPI_v1.c

    Also, if you are still looking for a way to force the SPI CS then look at the McSPICSAssert function in the Chip support library. This uses the FORCE bit in the MCSPI_CHXCONF to force the Chip enable between transactions. This can only be used in single channnel mode.

    Regards,
    Rahul