C6747 EMIFA Read External DPRAM (FPGA Internal) Speed ?

longbin qiao

Hi,
My C6747 Run @ 300M , CACHE :L1P=32K,L1D=32K,L2=64K.
EMIFA_CS4 Connected to the DPRAM(FPGA Internal), I use EDMA read DPRAM 800 bytes to L2_SRAM with 114 us .
I think this speed is still slow, How to improve the speed?

Setup_EMIFA:
    /* Setup CS4 - 8-bit normal async */
    AEMIF_A3CR = 0x00a00504; // Setup=0, Strobe=A, Hold=0, TA=1, 8-bit
    AEMIF_NANDFCR &= ~4;

EDMA code:
gEdma3ccRegs->PARAMSET[0].OPT = 0x00100008;
gEdma3ccRegs->PARAMSET[0].SRC = ( Uint32 )DPRAM_Addr ;
gEdma3ccRegs->PARAMSET[0].A_B_CNT = 0x00010000 + 800   ;
gEdma3ccRegs->PARAMSET[0].DST = (Uint32)gLineBuf;
gEdma3ccRegs->PARAMSET[0].SRC_DST_BIDX = 0x00000000;
gEdma3ccRegs->PARAMSET[0].LINK_BCNTRLD = 0x0000FFFF;
gEdma3ccRegs->PARAMSET[0].SRC_DST_CIDX = 0x00000000;
gEdma3ccRegs->PARAMSET[0].CCNT = 0x00000001;
gEdma3ccRegs->ICR =0x00000001;
gEdma3ccRegs->ESR =0x00000001; //enable EDMA_EVENT_0(start EDMA)

//wait Edma over...
while ( gEdma3ccRegs->IPR == 0) {};

Thanks !

over 14 years ago

0 tlee over 14 years ago

TI__Guru 62975 points

I suspect that the EMIF may be limiting your performance.

What is your reference clock frequency for EMIFA? Based on your settings, an individual byte access would take at least EMIFA_CLK_PERIOD / (1 + 11 + 1).

0 longbin qiao over 14 years ago in reply to tlee

Prodigy 50 points

Thanks for your response .

EMIFA clock driven by PLL SYSCLK3

Setup_PLL:

    /* Configure ARM, DSP at 300MHz, EMIFs at 133MHz */
    unsigned int DIV45_EN = 1;
    unsigned int CLKMODE = 0;
    unsigned int PLLM =   24;
    unsigned int POSTDIV = 1;
    unsigned int PLLDIV3 = 1;
    unsigned int PLLDIV5 = 5;
    unsigned int PLLDIV7 = 7;

but I change PLLDIV3 value :(eg. 1,2,3,), the Speed does not change... why?

0 Mukul Bhatnagar over 14 years ago in reply to longbin qiao

TI__Guru* 83935 points

Please make sure that writes to PLL are not locked via configuring the CFGCHIP0(bit 4)

Please make sure that if you are trying to change the SYSCLK divider values , you are following the procedure outlined in the system guide

http://focus.ti.com/lit/ug/sprufk4d/sprufk4d.pdf

Section 7.2.2.3

Regards

Mukul

0 RandyP over 14 years ago in reply to Mukul Bhatnagar

TI__Guru* 84110 points

longbin qiao said:
EMIFA_CS4 Connected to the DPRAM(FPGA Internal), I use EDMA read DPRAM 800 bytes to L2_SRAM    with 114 us .
I think this speed is still slow, How to improve the speed?
Setup_EMIFA:
    /* Setup CS4 - 8-bit normal async */

    AEMIF_A3CR = 0x00a00504; // Setup=0, Strobe=A, Hold=0, TA=1, 8-bit

tlee said:
Based on your settings, an individual byte access would take at least EMIFA_CLK_PERIOD / (1 + 11 + 1).

Taking the math here to completion, with a maximum EMIFA clock frequency of 100MHz or a period of 10ns, the time to transfer 800 bytes with your A3CR settings is

10ns * 800 read operations * 13 cycles per read = 104us

This is very close to what you are seeing. Is your question why you are seeing 114us instead of 104us? If so, then we need to know the frequency of the EMA_CLK pin and we need to know how you are measuring the 114us (code-based timer or oscilloscope/logic analyzer).

If you question is why it take more than 100us to transfer 800 bytes, then we need to discuss why you have set Strobe=A and see if you can go to a smaller number. If not, then this is the speed you will get.

0 longbin qiao over 14 years ago in reply to Mukul Bhatnagar

Prodigy 50 points

Thanks,

I can confirm is that CFGCHIP0 has been set right , CFGCHIP0 = 0x00000100 . the bit 4 is 0.

But the speed still no change. if I Select 4.5 divider for EMIFAclock source ,the speed changed.

Even if the setting is right, What is the maximum speed of EMIFA read form DPRAM(with EDMA )?

...

0 longbin qiao over 14 years ago in reply to longbin qiao

Prodigy 50 points

I change AEMIF_A3CR set:

eg:

AEMIF_A3CR = 0x00a00504; // Setup=0, Strobe=A, Hold=0, TA=1, 8-bit

AEMIF_A3CR = 0x00200504; // Setup=0, Strobe=2, Hold=0, TA=1, 8-bit
.....

the speed is not changed .

Now ,I want to improve the speed,How can I do?

Thanks.

0 longbin qiao over 14 years ago in reply to longbin qiao

Prodigy 50 points

I check the AEMIF_A3CR ( Configuration Register ) Field Descriptions,

I change the write Strobe time ,not the read Strobe time ,So the speed is not changed! :) o_o

0 RandyP over 14 years ago in reply to longbin qiao

TI__Guru* 84110 points

The register is not called A3CR on this device either, right? Is it supposed to be called CEnCFG?

When you change the Read Strobe time, do you get the changes you expect?

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C6747 EMIFA Read External DPRAM (FPGA Internal) Speed ?