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Is safe to write directly in an EDMA register from an EDMA transfer?

James Thorton
Expert 1390 points


Hello, I am using EDMA 3.0 in dm6437. I am using EDMA3 low level driver, and what I would like to do is perform an edma transfer to recharge Paramset.src of another channel. 

For example:

 

Channel 2:

Paramset.src= &BufferOut
Paramset.dst= McBSP_DXR

 Channel X:

unsigned int memoryPointerAddress= &BufferOut

Paramset.src= &memoryPointerAddress
Paramset.dst=&Paramset(2).src

         in this way every time that channel X perform its transfer it would update Paramset(2).src to point to begin of BufferOut that would be great for my application. What I wonder if this is sure for the application or I can have issues due to I am directly writting to an EDMA register. Typically I would do this using a Link channel, but the transfer does not have a constant size so I can set acnt,bcnt,cnt in order to perform a link in a right moment. So, this channel X would be tied to a GPIO that would tell me when I need to update the pointer to my buffer (I have an external signal to indicate that). I hope it has sense for you. Could someone told be anything about that?

Thanks in advance

 

  • 0
    TI__Mastermind 41665 points

    In general EDMA should be able to transfer to PaRAM, as PaRAM is just another piece of memory on the internal data bus, I have heard of this sort of thing being done on older devices before but I have never actually tried it myself. The main issue I would watch out for here would be caching like with any EDMA transfer, you have to ensure that the pointer you are copying into the PaRAM with channel X is actually updated in memory and not stuck in cache.

    If there is an event driving X and you are going to have to get a completion event interrupt from channel X to update the pointer to your buffer with the CPU anyway, than I do not see the benefit of doing this instead of just having an completion event interrupt from channel 2 that would update the pointer to the buffer directly with the CPU and avoid using one channel to configure another channel. Perhaps I am misunderstanding what you need to do?

     

  • 0 in reply to Bernie Thompson TI
    Expert 1390 points

    You get my idea, that's exactly what I want to do. I would avoid the issue that you talk if I simply allocate the pointer variable directly in Cache, wouldn't I?

  • 0 in reply to James Thorton
    TI__Mastermind 41665 points

    If the variable was allocated in internal memory you would not have the same caching problems, so yes (though technically the cache portion of internal memory is not addressable).

  • 0 in reply to Bernie Thompson TI
    Expert 1390 points

    Thanks bernie, but excuse me but I do not understand the last part of your comment..  what do you mean exactly with "the cache portion of internal memory is not addressable"

     

  • 0 in reply to James Thorton
    TI__Guru*** 125430 points

    Internal memory can be configured as either cache or SRAM.  When it is configured as cache then it is "owned" by the cache controller and not addressable by the CPU or any other peripherals.  When it is configured as SRAM then it can be used normally and can be written to by CPU and peripherals.