Part Number: AM3352
Tool/software: Linux
Hi there,
In the TRM I found the GPMC related time most can be configured to 31 gpmc_fclk value. But now my gpmc bus is not connect to a SRAM directly，but use a device (you can call it FPGA, although it a chip with MVB service) as a intermediary.
The cs, write, read signal will reach the chip as usual, when the chip judge the right access, it will send the corresponding signal to the SRAM. But because of the signal transfer, only set the GPMC cs-off, wr-off, oe-off , read access time, read&write cycle time longer, can the chip start to work and access MVB access.
In the previous device with the architecture (connect with a F28335 cpu by the XINTF bus) , the cs-off time is almost 600ns which the max cs-off time by AM335x is 310ns. I found the gpmc_fclk is 100mHZ, so the gpmc_fclk is 10ns, with 31 multiplier , the value will be 310ns.
Now I need the time longer, which way can I go? gpmc_fclk frequency division or wait signal usage? Please help me!!
