TMS320C6678: C6678 SRIO Gen 1 vs Gen 2 throughput

stephen li wai hung

Part Number: TMS320C6678

I would like to know the effective bandwidth of SRIO Gen 1 and Gen 2. , not the bitrate difference of SRIO Gen 1 and Gen 2

I found that there are number of doc. talk about throughtput

Throughput Performance Guide for KeyStone II Devices

http://www.ti.com/lit/an/sprabk5b/sprabk5b.pdf

Throughput Performance Guide for TCI66x KeyStone Devices

http://www.ti.com/lit/an/sprabh2a/sprabh2a.pdf

Throughput Performance Guide for C66x KeyStone Devices

e2echina.ti.com/.../Throughput-Performance-Guide-for-C66x-KeyStone-Devices-_2800_Rev.-A_2900_.pdf

And the SRIO througthput data is different ,

C6678, 1GHz is used , which is one is suitable for reference.

And what is SRIO data read latency in SL2, DDR3 in different playload size?

Thanks.

Stephen

over 7 years ago

0 Yordan Kovachev over 7 years ago

TI__Guru**** 161600 points

Hi Stephen,

For c6678 you should refer to Throughput Performance Guide for C66x KeyStone Devices.
I am looping the design team to elaborate.

Best Regards,
Yordan

0 Garrett Ding over 7 years ago in reply to Yordan Kovachev

TI__Mastermind 43296 points

Stephen,

The throughput benchmarks were obtained using different version of SRIO drivers. And as Yordan pointed out, for C6678 you should refer to Throughput Performance Guide for C66x KeyStone Devices.

For SRIO data read latency in in SL2 and DDR3, please refer to the section 3 Memory Access Throughput Performance and section 4 DDR3 Throughput.

Regards,
Garrett

0 stephen li wai hung over 7 years ago in reply to Garrett Ding

Prodigy 60 points

Hi,

I go through section 3 and section 4, I donot quite get the latency information of SRIO to SL2, DDR3.

please help to identify it.

Thanks.

Stephen

0 Garrett Ding over 7 years ago in reply to stephen li wai hung

TI__Mastermind 43296 points

Stephen,

I probably mis-understood your question about SL2/DDR3 memory access latency. Are you looking for the C6678 SRIO DirectIO read/write latency with data in SL2/DDR3 as shown in table 16-19 of SPRABK5B.pdf for keystone 2 device? Instead of data read/write from/to the buffers associated with CPPI host descriptor.

Regards,
Garrett

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TMS320C6678: C6678 SRIO Gen 1 vs Gen 2 throughput