Part Number: AM5728
Tool/software: TI-RTOS
HI! When I configure the MCASP (DATA port \ 4slot TDM)，I have a problem.
After write the first data to XBUF ,TXSTAT[5]XDATA is always 0. why?
I'm very grateful to you for your help.
my code :
void McaspTxInternalInit(uint32_t baseAddr)
{
//Global Initialization
McaspGlobalReset(baseAddr);
//2. Configure the FIFO.
McASPWriteFifoDisable(baseAddr); //NO FIFO
McASPReadFifoDisable(baseAddr); //NO FIFO
//3. Configure the local power management.
McASPSetPowerIdleConfig(baseAddr, MCASP_IDLEMODE_NOIDLE); //0x1: No-idle mode
//4. Configure the transmit format unit.
McASPTxFmtMaskSet(baseAddr, TXMASK32); //NO MASK
McASPTxFmtSet(baseAddr, MCASP_TX_SYNC_DELAY_2BIT | MCASP_TX_BITSTREAM_LSB_FIRST |
MCASP_TX_PAD_WITH_0 | MCASP_TX_SLOTSIZE_32BITS |
MCASP_TX_BUF_DMAPORT | MCASP_TX_ROT_RIGHT_NONE); //1 bit delay, LSB first, no PAD, 32bit slot, (PERICONFIGPORT)
//5. Configure the transmit frame sync generator.
McASPTxFrameSyncCfg(baseAddr, 0x4, MCASP_TX_FS_WIDTH_WORD, MCASP_TX_FS_INT_BEGIN_ON_RIS_EDGE); //4slot, single bit
//6.1 Configure the transmit clock generator.
McASPTxClkCfg(baseAddr, MCASP_TX_CLK_INTERNAL, TXMIXCLKDIV_1, TXAUXCLKDIV_2);
McASPTxClkPolaritySet(baseAddr, MCASP_TX_CLK_POL_RIS_EDGE); McASPTxHFClkPolaritySet(baseAddr, MCASP_TX_HI_FREQ_CLK_NO_INVERT); //6.2 Configure the transmit clock failure detect logic //TODO
//7. Program all bits - XTDMSk.
McASPTxTimeSlotSet(baseAddr, 0x0000000F); // TDMslot 0123 active
//8. Configure the desired n-th serializer for transmit mode operation.
McASPSerializerTxSet(baseAddr, TXAXR3);
//9. Setup all active transmitters to operate in TDM mode.
McASPDITModeCtlWrite(baseAddr, MCASP_TXDITCTL_DITEN_DISABLE);
//10. Configure the MCASP pins functionality.
McASPPinMcASPSet(baseAddr, MCASP_PIN_AFSX| MCASP_PIN_ACLKX| MCASP_PIN_AXR(3));
//Configure the MCASP pins direction
McASPPinDirOutputSet(baseAddr, MCASP_PIN_AFSX); McASPPinDirOutputSet(baseAddr, MCASP_PIN_ACLKX); McASPPinDirOutputSet(baseAddr, MCASP_PIN_AXR(3));
//11. Optional : Configure a MCASP Tx channel for loopback operation (TDM mode only) in MCASP_LBCTL [31:0].
// no LOOPBACK
//12. Release from reset state the divider that outputs the AHCLKR clock.
//13. Poll the bit to ensure that it is successfully latched in the register.
//14. Release from reset state the divider that outputs the ACLKR clock.
//15. Poll the bit to ensure that it is successfully latched in the register.
McASPTxClkStart(baseAddr, MCASP_TX_CLK_INTERNAL);
//Global Initialization END
//Operational Modes Configuration
McaspTxPollingMethod(baseAddr);
//Operational Modes Configuration END
}
