EMIF interface

jalexander

Have a 16 bit emif interface to an FPGA.

Default from the kernel is 32 bit access.

Need to set to 16 bit alignment/access.

Not sure if this is a function of the kernel or u-boot.

Can someone point me in the right direction?

0 Juan Gonzales over 16 years ago

This is likely at the u-boot level; I believe the SDRAM (DDR2 controller) initialization happens there.

0 jalexander over 16 years ago in reply to Juan Gonzales

Juan,

Some more details.

We have a 16 bit emif interface off of CS5, 0x08000000.

Using mmap on /dev/mem does not return 16 alignment.

So this is not DDR2 related.

Processors forum