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what is balanced/unbalanced clock?

Zhiliang.Chen
Intellectual 470 points

There is a saying in the spec:

The clocks derived from CORE_CLK are fully balanced over the device.

The 96M_FCLK, 48M_FCLK, and 12M_FCLK clocks are functional unbalanced clocks for a number of
modules in the CORE and PER power domains.

what does balanced/unbalanced mean?

 

  • 0
    TI__Guru 59235 points

    A balanced clock will have minimum timing skew across the device.  An unbalanced clock has not been optimized to minimize clock skew across the device.  

     

    Minimizing clock skew is important for synchronous logic circuits, but may not be required for circuits designed to be asynchronous.

     

    Regards,

    Paul

     

  • 0 in reply to peaves
    Genius 3685 points

    To make it 100% clear. The difference between a balanced and an unbalanced clock system is basically not important for any kind of end-user-usage of the chip, but very important for the chip designers in order to account for propagation delays through different paths internally in the chip.

    Best regards
      Søren

  • 0 in reply to Soren Steen Christensen
    Intellectual 410 points

    Dear All,

    I have a related query on 48M_FCLK. We have a system with support for suspned/resume. During suspend state, we put CORE clock to 48 MHz and during resume we move back the CORE clock to 200 MHz. After resume we observe that USB HOST domain (EHCI controller) and SPI2 are not functioning in expected way. Tracing back the root cause we observed that 48M_FLCK is being used by both the modules.

    Can any of you have observed such issues related to 48M_FLCK?
    Why does 48M_FLCK have dependency on CORE clock?

    If any one of you have inputs or observations, please share.

    Thanks,

     

    Regards,

    ~Ajit

  • 0 in reply to ajit basarur
    TI__Guru 65405 points

    I was not observe such issue related to 48M_FLCK, but

    There are several ways to analyze the problem:


    1. You can use the TI Clock Tree Tool (CTT). It is software used to understand the complex clock framework dependencies on OMAP chips. It could be helpful to trace all clock dependencies - the way from the oscillator on the board to the clocks in the IP functional block of interest.
    You can download the TI Clock Tree Tool from the following link:
    http://omappedia.org/wiki/CTT

    2. During suspend many of peripheries are reset and when resume the system they should be configured again. You should check necessary settings in resuming process.

    3. You can find useful information about the clocks in directory /d/clock/...  if you use ICS.