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TMS320C6748: Simulator cycle count vs actual hardware cycle count

Avi Tal
Expert 1120 points
Part Number: TMS320C6748


Dear Friends,

We are running some algorithm on the "cycle accurate simulator" and on real LCDK target at 456MHZ.

The cycle count on the target board is roughly twice as much as on the simulator.

We have maximum L1 and L2 open (256K).

Any suggestions why this can occur?

Thanks,

Avi Tal

  • 0
    TI__Guru**** 161600 points
    Can you share which SDK are you running on the LCDK? Or is this a custom bare metal algorithm?

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Expert 1120 points

    Dear Yordan,

    Thanks allot for your answer.

    We are running bare-metal algorithm.

    We are also aware that the simulator assumes zero-wait-state memory and does not simulate L2/DDR latency, so we are not surprised by the results.

    We just want to make sure there is nothing else we are missing.

    Thanks,

    Avi Tal

  • 0 in reply to Avi Tal
    TI__Guru** 116170 points
    Yes, the additional latency is expected but I am little surprised that the latency is twice of values observed on the simulator. Are you measuring performance using TSCH/TSCL registers?

    Can you confirm L1 Cache is enabled and all your data and code is in L2 ? Also make sure that your data buffers are aligned to cache line boundary.