Linux/DRA77P: XIP boot from 256MB NOR not working after a warm reset

Francesco Valla

Part Number: DRA77P

Tool/software: Linux

Hi,

I have a custom board based on J6P, booting in XIP mode from a 256MB NOR connected to GPMC.

While it's all working in cold boot mode and when issuing a cold reboot, the board does not start after a warm reboot. After a brief HW analisys, I found that GPMC_A27 pin in held HIGH after a warm reboot, causing the processor not finding the SPL.

If I place a copy of the SPL at relative offset 0x8000000 (128M) inside the NOR flash device, the board is able to boot (but I cannot follow this path, since this copy would overlap another partition).

I need the warm reboot feature for conditional reboot through SAR RAM.

Is this a know issue? Is there any solution/workaround?

Thank you

Regards,

Francesco

over 7 years ago

0 Stanislav Stilyanov over 7 years ago

TI__Mastermind 18030 points

Hi Francesco,

What is your sysboot pins configuration?

Thanks,

Stan

0 Francesco Valla over 7 years ago in reply to Stanislav Stilyanov

Intellectual 570 points

Hi Stan,

my sysboot configuration is the following:

SYSBOOT15 = 1
SYSBOOT14 = 0
SYSBOOT13 = 1
SYSBOOT12 = 0
SYSBOOT11 = 0
SYSBOOT10 = 1
SYSBOOT9 = 0
SYSBOOT8 = 1
SYSBOOT7 = 1
SYSBOOT6 = 0
SYSBOOT5 = 1
SYSBOOT4 = 1
SYSBOOT3 = 0
SYSBOOT2 = 1
SYSBOOT1 = 0
SYSBOOT0 = 1

Thanks,

Francesco

0 Stanislav Stilyanov over 7 years ago in reply to Francesco Valla

TI__Mastermind 18030 points

Francesco,

Can you try with sysboot15 = 0? The following will apply:

"0- Software re-configuration of pull resistors is allowed. Internal pull-downs on gpmc_a[n:19]
are enabled by default to allow GPMC boot. Pulling low gpmc_a[n:19] is required in order
to access the low-order address locations in the flash memory during boot (n = [27:24,
22:19] and depends on the memory volume)."

Regards,

Stan

0 Francesco Valla over 7 years ago in reply to Stanislav Stilyanov

Intellectual 570 points

Hi,

unfortunately, changing sisboot15 to 0 did not help.

Pull-down resistors are enabled, as confirmed by CTRL_CORE_BOOTSTRAP:

devmem2 0x4a0026c4
Memory mapped at address 0xb6f97000.
Read at address 0x4A0026C4 (0xb6f976c4): 0x000025B5

But still I'm not able to perform a warm reboot.

Thanks,

Francesco

0 Manfred Becker over 7 years ago in reply to Francesco Valla

TI__Expert 4570 points

Francesco,

could you provide data of the CTRL_CORE_PAD_GPMC_A27 register (address 0x4A0034AC) for the failing case?

0 Francesco Valla over 7 years ago in reply to Manfred Becker

Intellectual 570 points

Hi,

CTRL_CORE_PAD_GPMC_A27 register, read with the XDS200, is always 0x00040000, both in working and failing case.

0 Rajesh Vanga over 7 years ago in reply to Francesco Valla

TI__Intellectual 1350 points

Hi,
for GPMC XIP boot mode ROM only configures address lines GPMC_A18:A0, so I would suspect beyond ROM primary boot pad config of GPMC_A27 is configured to 1 by code, because of which on a warm reset you are observing GPMC_A27 set to 1. if you have a control for warm reset can you try setting GPMC_A27 to 0 via pad config and then assert warm reset..?

Thanks,
Rajesh Vanga

0 Francesco Valla over 7 years ago in reply to Rajesh Vanga

Intellectual 570 points

Hi,

this seems to solve my issue. I'm attaching the applied patch.

Thank you

Regards,

Francesco

Fullscreen 0001-ARM-DRA7xx-introduce-a-workaround-for-GPMC-warm-rebo.patch.txt Download

From 33eb02a783f3b78f8d5c2f698f0ca681f9005bbd Mon Sep 17 00:00:00 2001
From: Francesco Valla <francesco.valla@mta.it>
Date: Fri, 23 Mar 2018 16:12:50 +0100
Subject: [PATCH] ARM: DRA7xx: introduce a workaround for GPMC warm reboot

Since GPMC_A27 is set high when warm-rebooting, a workaround
is introduced in order to be able to warm-reboot from
GPMC-connected devices larger than 128MB.

Signed-off-by: Francesco Valla <francesco.valla@mta.it>
---
 arch/arm/mach-omap2/Kconfig         | 8 ++++++++
 arch/arm/mach-omap2/control.h       | 3 +++
 arch/arm/mach-omap2/omap4-restart.c | 7 +++++++
 3 files changed, 18 insertions(+)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 0fa15db..87ff26e 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -253,6 +253,14 @@ config OMAP5_ERRATA_801819
 	  a snoop from completing. Under certain conditions this can cause the
 	  system to deadlock.
 
+config OMAP5_GPMC_A27_WARM_REBOOT
+	bool "Support warm reboot from GPMC when using A27"
+	depends on SOC_OMAP5 || SOC_DRA7XX
+	help
+	  Since GPMC_A27 is set high when warm-rebooting, this option introduces
+	  a workaround in order to be able to warm-reboot from GPMC-connected
+	  devices larger than 128MB.
+
 menu "Reserve peripherals to other cores"
 	depends on SOC_OMAP5 || SOC_DRA7XX
 
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index 46ea820..f59d262 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -297,6 +297,9 @@
 #define DRA7_CTRL_CORE_BOOTSTRAP	0x6c4
 #define DRA7_SPEEDSELECT_MASK		(0x3 << 8)
 
+/* DRA7XX CONTROL CORE PAD */
+#define DRA7_CTRL_CORE_PAD_GPMC_A27	0x14ac
+
 /*
  * REVISIT: This list of registers is not comprehensive - there are more
  * that should be added.
diff --git a/arch/arm/mach-omap2/omap4-restart.c b/arch/arm/mach-omap2/omap4-restart.c
index 15e7126..b29a71b 100644
--- a/arch/arm/mach-omap2/omap4-restart.c
+++ b/arch/arm/mach-omap2/omap4-restart.c
@@ -10,6 +10,7 @@
 #include <linux/types.h>
 #include <linux/reboot.h>
 #include "common.h"
+#include "control.h"
 #include "prm.h"
 #include "omap4-sar-layout.h"
 
@@ -41,6 +42,12 @@ static void omap4_sar_ram_write_boot_mode(const char *cmd)
 void omap44xx_restart(enum reboot_mode mode, const char *cmd)
 {
 	omap4_sar_ram_write_boot_mode(cmd);
+
+#ifdef CONFIG_OMAP5_GPMC_A27_WARM_REBOOT
+	/* FIX for GPMC_A27 not being initialized with value 0 */
+	omap_ctrl_writel(0x0004000E, DRA7_CTRL_CORE_PAD_GPMC_A27);
+#endif
+
 	if (mode == REBOOT_COLD) {
 		omap_prm_cold_reset_system();
 	} else {
-- 
2.7.4

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Linux/DRA77P: XIP boot from 256MB NOR not working after a warm reset