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DRA750: Integrating ASRC using ATL

Rajan B
Prodigy 40 points
Part Number: DRA750


We are trying to integrate ASRC module to DRA75x using ATL(for ratio calculation). The ASRC module is getting input through McASP6 and writing the converted output to McASP3. My queries are:

1. Is it possible to use the ATL module in our case because McASP6_FSR is not available as the input to the ATL (Figure 31-2. ATL Integration) from the DRA75x TRM?

2. If we cannot use ATL for our use case, Is there any other module in DRA75x which can be used for integrating ASRC module?

  • 0
    TI__Expert 4570 points
    Are you using the McASP6 transmitter with independent bit clock and frame sync signals? It not, you could configure McASP6 to operate in synchronous mode and only use the ACLKX and FSX signals.

    If asynchronous operation of McASP6 is needed, you could still connect the FSR signal to one of the XREF_CLKx pins (if one of these pins is available) and select it in the source multiplexers of the ATL module.
  • 0 in reply to Manfred Becker
    Prodigy 40 points
    Thank you for your quick reply.
    I am currently not using McASP6 transmitter and only using McASP6 receiver. From your answer, I need to set ASYNC to 0b0 to set the McASP6 to work in synchronous mode and then the trasmitter will share the same bit clock and frame sync clock with receiver. Hence I can receive the data through McASP6, without transmitting anything. In this scenario as both McASP6_FSX and McASP6_FSR are having same signal, I can use McASP6_FSX as the input to the ATL module to get the ratio. Is my understanding correct?
    I have one doubt: If the above understanding is correct, do I need connect the LR clock with McASP6_FSX rather than McASP6_FSR?
    Please correct me if I am wrong.
  • 0 in reply to Rajan B
    TI__Expert 4570 points

    If using MCASP6 in synchronous mode, transmitter and receiver are only using the signals MCASP6_ACLKX and MCASP6_FSX.for bit clock and frame sync. You need to be aware the MCASP6_ACLKX signal will be inverted before used as bit clock for the receiver. Below is some extract from TRM on this topic.

    When MCASP_ACLKXCTL[6] ASYNC is written to 0b0, the transmit and receive sections operate
    synchronously to the transmit section clock and transmit frame sync signals.
    Though Rx section may have a different data format, it has to be configured to have the same slot size
    than the transmit section one. As shown on the Figure 24-116, with the ASYNC bit set to 0b0, the RCLK
    becomes an inverted version of the transmit clock generator XCLK output.

    In your case using synchronous instead of asynchronous mode wouldn't require any HW change because for MCASP6 the ACLKX/ACLKR as well as the FSX/FSR signals are using the same pads. Means, you just need to change the respective pad control registers to select the transmitter bit clock and frame sync instead of the receiver ones.

  • 0 in reply to Manfred Becker
    Prodigy 40 points
    Thank you for your quick reply.
    I have two queries for this implementation:
    1. As mentioned in the TRM, "the RCLK becomes an inverted version of the transmit clock generator XCLK output.". Do I need to configure any register to correctly receive the data like 'MCASP_ACLKRCTL.CLKRP' or any other register?
    2. As you mentioned, I need to configure the pad control register to select ACLKX,FSX. The pad control registers are CTRL_CORE_PAD_MCASP1_AXR10 (MCASP1_AXR10_MUXMODE = 0x1 (mcasp6_aclkx)) and CTRL_CORE_PAD_MCASP1_AXR11 (MCASP1_AXR11_MUXMODE=0x1 (mcasp6_fsx)).
    a. Is my understanding correct?
    b. If this is the case, I won't be able to use Audio transmit/receive data - channel 10 and 11 (McASP1_AXR10 and McASP1_AXR11) of McASP1. Is my understanding correct?
    Thanks in advance.
  • 0 in reply to Rajan B
    TI__Expert 4570 points

    1. It's common to operate McASP transmitter and receiver on opposite clock edges. In any case you need to validate if the McASP input timing requirements are met based on the output timings of your transmitting device. In your use case (not using McASP6 transmitter) you're free to select the active bit clock edge for the receiver by configuring 'MCASP_ACLKXCTL.CLKXP.'. Be aware the active receiver clock edge is always the opposite to what's selected by this CLKXP bit. In MCASP synchronous mode the configuration bit 'MCASP_ACLKRCTL.CLKRP' is not used.

    2. Yes, it's correct you need to configure the CTRL_CORE_PAD_MCASP1_AXR10 and CTRL_CORE_PAD_MCASP1_AXR10 for selecting the mcasp6_aclkx and mcasp6_fsx signals. In that case pad B13 cannot be used for mcasp1_axr10 anymore, but there's still the option to use pad F21 for mcasp1_axr10 instead. Signal mcasp1_axr11 isn't available anymore if using pad A12 for the mcasp6_fsx signal.