RTOS/AM5728: PCIe bar memory mapping

The RTOS team have been notified. They will respond here.

Hi,

What software and version you are referring to the issue? The OB size concept is only applicable to Keystone PCIE, but not AM57x device.

If you look at the PCIE example with TI RTOS, processors.wiki.ti.com/.../Processor_SDK_RTOS_PCIe, there is already how to setup outbound translation in pcieObTransCfg().

Regards, Eric

I am using TI pdk 4.0.0.4. My RC is DSP and EP is FPGA.

I am working as RC. I am doing outbound adress translation as present in pcie example code only. The concern is how to map 2GB bar0 memory of EP in RC.
And what should be the RC mask register value. Its 256MB in the example code. I am changing it to 2GB.
The outbound translation i am doing is as follows.

0x21000000 mapped to 0xA0000000 EP bar address which is programmed by RC as part of enumeration.
The size of outbound translation function is 1MB
How 2GB memory is mapped?

Hi,

You only have a 256MB memory window for the AM572x PCIE, this is the maximum you have. You can't use it to access 2GB memory of the remote side. If your FPGA has 2GB range to access and if your FPGA has inbound translation mechanism, you can have several BARs on the EP side and each mapping to a different regions.

Regards, Eric

The FPGA is now providing 2 bars of size 4KB and 128KB. bar0 i have programmed 0xFE400000 and bar1 is programmed 0xFE500000

I have configured my outbound address translation as below

0x21000000 ---> 0xFE400000  size 0x00000FFF

0x21100000 ---> 0xFE500000 size 0x 0001FFFF

Confirm me whatever I am doing is correct.

I am curious to know what should be done at the FPGA end because I am not able to read/write in both the BARs

Also If bar0 memory is 2GB, then how i can configure the address translation. Please let me know as this is what the FPGA team is giving as they are not able to do address translation. The FPGA team wants to keep direct addressing for different memories with different offsets

Hi,

"I am curious to know what should be done at the FPGA end because I am not able to read/write in both the BARs"

In TI pcie example, there are two memory mapping regions:
OB region 0 used to access remote EP configuration space offset 0x1000 with 4KB window
OB region 1 used to access remote EP memory space offset 0x0100_0000 with 16MB window

I wonder if you follow TI's method, are you able to access the FPGA's PCIE configuration registers from the OB region 0? Are you able to read the FPGA's BAR0 and BAR1?

Regards, Eric

At ob region 0 offset 0x0001000 i am able to read fpga's pcie configuration space have read the vendor id device id properly.

After that i have configured region 1 of 4kb at offset 0x01000000 and region 2 of size 128kb at offset 0x01100000.

My bar0 and bar1 are mapped to region 1 and 2.

I am not able to access these memory

Is my implementation correct?

Hi,

For the AM572x (RC) side, the OB 0 setting looks correct.
For OB 1, you mapped offset 0x0100_0000 -----> to 0xFE400000 size 0x00000FFF
For OB 2, you mapped offset 0x0110_0000 ------> to 0xFE500000 size 0x 0001FFFF
It should work.

For the FPGA side, you have BAR0 ans BAR1, it configured as:
BAR0: 0xFE400000
BAR1: 0xFE500000
Is that correct?

Right after Dev and vendor ID register, there is one called STATUS_COMMAND, did you programmed that? You may try a value of 0x100146 to see if it helps?

Regards, Eric

Any news?

Regards, Eric