Part Number: AM5728
Tool/software: TI-RTOS
Hi I have an RF device RF 20252 connected to AM 5728 on SPI. Im trying to write a slave driver for this RF. The AM5728 is connected using only 3 wires, only chip select, clk and data (either D0 or D1) from AM 5728 to RF. Given below is the diagram showing interfacing of the rF device to a typical controller and the corresponding write and read timing diagrams.
As shown in the diagram above, the chip select has to go low after 1 clock cycle and remain low for the entire transaction. In case of the write transaction, a start bit is followed by a 0 to indicate write transaction, followed by the actual Address and data. The read follows a similar pattern with the difference that after the address is sent, the driver will get the read data only after 2 clock cycles. Following are the questions that i had:
a>Will the above protocol be supported by SPI master on AM 5728?
b>How do i ensure that Chip select is delayed by 1 clock cycle?
c>Only 1 data line gets used for read as well as write. Does this mean i have to use the SPI master in half duplex mode? In case of read, it means i first set up the SPI master in tx_only mode to write the address and then set it up in rx_only mode to read the data?
d>Is there any reference example available for similar usage of SPI? the PDK example does not use SPI in the same manner?
