AM3359: DDR3 routing question

varun Rajamanickam

Part Number: AM3359

I understand the AM3359 datasheet section 7.7.2.3 covers the routing guidelines for DDR3 placement, length, spacing between nets etc..

Is there any guideline / recommendation available for Serpentine / Meandering Routing for DDR3 signals? what will be the appropriate space between the serpentine loops that are in parallel (same net)?

Regards

Varun R

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

There is no such recommendation. A good advice is to follow the same spacing as the one used between two signals of the same class.

0 Ajit Nandakumar Mannargudi over 8 years ago in reply to Biser Gatchev-XID

Prodigy 70 points

Hi ,

Hi,

I am Varun's colleague working on this topic. In DDR3 designs, this parameter of spacing within the serpentine is important because it is can change the velocity of the signal. Many specifications mention 5W or 4 W (w=width of trace). The spacing within a class is quite less compared to this. I believe there has to be a specification/guideline for this as it is mandatory for all DDR3 designs. So it would be great if you could provide more details on this. Since TI has done the simulation part to provide the specs, it would be very useful if TI provides rationale on serpentine spacing.

Thanks

Regards,

Ajit

0 Biser Gatchev-XID over 8 years ago in reply to Ajit Nandakumar Mannargudi

TI__Guru**** 393215 points

Simulations are board-specific. You can refer to the EVM boards layout files for guidance: processors.wiki.ti.com/.../AM335x_Boards

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AM3359: DDR3 routing question