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what dose CLKINP refer to?

Zhiliang.Chen
Intellectual 470 points
Other Parts Discussed in Thread: OMAP3530

what dose CLKINP refer to?

It is in the "DPLL Jitter Correction" section about setting the XXX_DPLL_FREQSEL.

The internal clock frequency is the frequency of the internal interface clock Fint, with Fint=
(CLKINP/(N + 1).

And the CORE_DPLL_FREQSEL description is: This bit field allows selecting the proper range of the DPLL3 internal frequency depending on the DPLL reference clock and the N divider.

we're now have 26Mhz square clock connected to the device(sys_xtalin), and it is divided by 2, so it becomes 13Mhz(SYS_CLK) and supplies to the DPLL3 as reference clock.
The DPLL3 divider factor is 12. so:

Fint_DPLL3 = (13Mhz/(12+1)) = 1Mhz.

But the code in the BSP sets CORE_DPLL_FREQSEL to 7 which is 1.75 MHz to 2.1 MHz. Why?

  • 0
    TI__Expert 4155 points

    In WINCE BSP, SYS_CLK is 26MHz. The system clock divider in PRM_CLKSRC_CTRL[7:6] is set to 1 not 2.

    So Fint_DPLL3 = (26MHz/(12+1)) = 2MHz. It is in the range of 1.75MHz to 2.1MHz.

    The system clock divider can be read from the system by using the following command:

    \> do in32 48307270

    48307270: 00000050

    Bit 7:6 gives divider = 1.

    -Tao

     

  • 0 in reply to Tao Zhang
    Intellectual 470 points

    if the  SYS_CLK  is not divided by 2, due to the settings in platform.c the MPU clock will be 1.2GHz.

    we have the following configurations:

    #define BSP_SPEED_CPUMHZ                600

    #define BSP_MPU_DPLL_MULT           ((BSP_SPEED_CPUMHZ / 2) << 8)   // Multiplier
    #define BSP_MPU_DPLL_DIV            (12 << 0)                       // Divider

    #define BSP_MPU_CLK_SRC                (2 << 19)    // DPLL1 bypass = CORE.CLK/2

    then MPU_CLK = (26MHz*2*(600/2)) / (12+1)  = 1200Mhz. That's so confusing..

     

     

  • 0 in reply to Zhiliang.Chen
    TI__Genius 16690 points

    MPU_CLK is a clock source to MPU subsystem. ARM Cortex-A8 core is driven by ARM_FCLK generated inside MPU subsystem. The MPU_CLK is divided by 2 in the MPU subsystem to generate ARM_FCLK. This divider is active only when the DPLL is locked. Please refer Figure 3-3. MPU Subsystem Clocking Scheme and Table 4-56. Processor Clock Configurations in OMAP3530 TRM (SPRUF98I–April 2010–Revised August 2010) for the details.