what dose CLKINP refer to?
It is in the "DPLL Jitter Correction" section about setting the XXX_DPLL_FREQSEL.
The internal clock frequency is the frequency of the internal interface clock Fint, with Fint=
(CLKINP/(N + 1).
And the CORE_DPLL_FREQSEL description is: This bit field allows selecting the proper range of the DPLL3 internal frequency depending on the DPLL reference clock and the N divider.
we're now have 26Mhz square clock connected to the device(sys_xtalin), and it is divided by 2, so it becomes 13Mhz(SYS_CLK) and supplies to the DPLL3 as reference clock.
The DPLL3 divider factor is 12. so:
Fint_DPLL3 = (13Mhz/(12+1)) = 1Mhz.
But the code in the BSP sets CORE_DPLL_FREQSEL to 7 which is 1.75 MHz to 2.1 MHz. Why?