AM3352: DDR3 routing rules

Nick Yen

Prodigy 30 points

Part Number: AM3352

Hi there,

I know the data sheet has mentioned the DDR3L layout guidelines, but there are somethings are not clear to me.

Would like to know below information.

1.) Should CLK be controlled as 100 ohm diff pairs?

CK/CKn , UDQS/UDQSn , LDQS/LDQSn

What is max length on CLK?

How about length matching for same pair?

How about length matching for pairs to pairs?

2.) Should address line be controlled as 50 singled ended?

What is max length on address line?

How about length matching for each address line?

How about length matching for address vs clock ? do we need it ?

3.) Should data line be controlled as as 50 singled ended?

What is max length on data line?

How about length matching for each data line?

How about length matching for data vs clock ? do we need it ?

Thanks

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

Hi,

CK/CKn , UDQS/UDQSn , LDQS/LDQSn are all 100Ohm differential pairs. Length doesn't need to be matched between CK/CKn, UDQS/UDQSn and LDQS/LDQSn pairs. However CK pair must be length matched to Address/Control net class, and UDQS/UDQSn, LDQS/LDQSn pairs must be length matched to their respective data lanes.
All single-ended lines are 50Ohm. All the other information you request is available in Table 7-66 and Table 7-67 in the datasheet.

0 Nick Yen over 8 years ago in reply to Biser Gatchev-XID

Prodigy 30 points

Hi there,

Thanks for rapid reply.
Table 7-66,
What does AS mean?
What does AT mean?

Figure 7-67
Have a specific number for DQLMX0 / DQLMY0/ DQLMY1 ?

0 Biser Gatchev-XID over 8 years ago in reply to Nick Yen

TI__Guru**** 393215 points

For details of Table 7-66 look at Figure 7-66.
No, there are no specific numbers for Figure 7-67.

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AM3352: DDR3 routing rules