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IPU AMMU & unicache

Guy Mardiks
Genius 4135 points

Hello,

1. when cache is enabled (NOT bypassed on the CACHE_CONFIG register) and a page is active, is it OK to enable and disable the cached/non-cached attribute on an AMMU page policy register while currently running and using (program & data) the same page (both PC and SP ,...  are within the page) if writing back all dirty lines and invalidating the cache prior  to disabling it (bit 16 on the policy register)?

The mapping for the CPU will stay the same but is there something else that might forbid doing so?

2. Regarding AMMU - i understand that smaller pages have priority over larger ones when they have overlapping regions. what i am not sure is what happens if if have for example two large pages with overlapping regions but different attributes? what if one of the large pages is configures with the larger page size and the other to the smaller - i.e one large page is 512M and another 32M and the range of the 32M page is inside the 512M page? will the 32M take priority or is it illegal?

Thanks

Guy

  • 0
    TI__Guru 55685 points
    Hi Guy,
    1. It is not the best practice to do change policy register of a page when both SP and PC are within the page. Can you provide more details on the requirement.
    2. This is illegal as both pages should have the same priority which will cause a page fault.
    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Genius 4135 points

    Hi,

    I am considering my options imposed by limitations of the AMMU - very limited number of pages and pages sizes and there after the 512M the next size only is 32M.

    I have one application that needs to call another, where i wanted to have cache enabled in region >32M which resides inside a region of 512M. since i am not able to do that i was considering enabling the cache of the entire 512M page for the first application and before calling the second, disabling the cache for that page (both applications are running also within that page). the second application should not have cache enabled on most of that region.

    (if i could have enabled cache inside the 512M but for region that is larger than 32M this could also have been a solution - but this seems to be impossible).

    Thanks

    Guy

  • 0 in reply to Guy Mardiks
    TI__Guru 55685 points
    Hi Guy,

    You can solve this issue by using same approach as Vision SDK. You can use two large pages for mapping to same physical address. E.g. Map 0x8000_0000 to 0xA000_0000 and 0x8000_0000 to 0x8000_0000. Make one of them cacheable and other as non cacheable.
    Do you see any constraints on your system with this approach.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Genius 4135 points

    Hi, thanks.

    This is the approach i was going to take except i intend to map a large page to virtual address 0 ( 0 --> 0xE0000000) + small/medium page that maps the RAM to 0 also  (that will take priority).

    I was just trying to see if i can somehow avoid having to set a run address different from the load address.

    do you see any problem with mapping the the large page to zero (i don't see this region being used for anything else (in our case) )

    Thanks

    Guy

  • 0 in reply to Guy Mardiks
    TI__Guru 55685 points
    Hi Guy,

    Mapping 0x0 to 0xE000_0000 should be fine. I am assuming you want to map 32 MB page here.
    The care about is that first 1 MB has IPU internal mappings and hence you can only use only remaining 31 MB area.
    You will also need to update the DMM for the same for accesses via L3.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Genius 4135 points
    Hi,
    I am planning to map a full 512Mb page of DDR space to 0 (where first addresses will be mapped to RAM).
    From IPU i see only the first 16K are marked as internal (and they will be mapped the RAM ). as for the 1MB of E0000000 i will not be using the virtual addresses mapped to these for DDR access - i needed to include them in the mapping since i need page address aligned to 512M
    I am not sure why i will need to update DMM - from DMM perspective the addresses will still be regular L3 DDR addresses in the range of 80000000 - FFFFFFFF (AMMU is doing the translation before is reaches DMM) - am i missing something?

    Thanks
    Guy
  • 0 in reply to Guy Mardiks
    TI__Guru 55685 points
    Hi Guy,

    The AMMU mapping use seems fine.
    DMM comment is not related to AMMU/IPU.
    You need to update DMM i.e. LISA map for accessing more DDR.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Genius 4135 points

    Hi, thanks.

    DMM & LISA have already been configured for the whole 2Gb DDR accessible range starting from 0x80000000 .

    Thanks

    Guy