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RTOS/TMS320C6674: Problem disabling L1D cache in RTSC platform

Butters
Expert 2021 points

Part Number: TMS320C6674

Tool/software: TI-RTOS

Hello,

I am running into a problem with the way that L1D cache is disabled through a RTSC platform (accessed in CCS via Project -> RTSC Tools -> Platform -> Edit/View). I have an intermediate bootloader executing on core 0 that loads a SYS/BIOS application onto core 2. This SYS/BIOS application has initialized variables that are located in L1D memory. When I step through the execution of _c_int00() on core 2, I find that _auto_init_elf() is executed before the cache settings in the RTSC platform are applied. Therefore, the variables that are located in L1D memory are initialized, but then they are later being overwritten because the L1D memory is still being used as cache. It really seems like the cache settings in the RTSC platform should be applied before _auto_init_elf() is executed!

So the immediate problem that I have is the fact that these initialized variables in L1D memory are being "corrupted." I am looking for an easy workaround for this problem. Some questions that I have are:

  1. Is there any way to change the L1DCFG register of another core from my intermediate bootloader that is executing on core 0?
  2. Is there any way that I can "hook" into the very beginning of the _c_int00() code of my SYS/BIOS application to manually set the L1DCFG register before _auto_init_elf() is executed?

I can't imagine that I'm the first person to run into this problem, but I didn't find anything relevant by searching the forums. Thanks in advance for your attention to this problem. Have a good day!

Best regards,
Dave

  • 0
    TI__Guru**** 161600 points
    Hi Dave,

    We're looking into this.

    Best Regards,
    Yordan
  • 0
    TI__Mastermind 37985 points
    Dave,
    this is an old thread, so I am not sure if it's relevant but talks about the same problem you are having:
    e2e.ti.com/.../400333
    The advice seems to be to use L1D memory only for uninitialized sections.
  • 0 in reply to Sasha Slijepcevic
    Expert 2021 points

    Hi Sasha,

    Thank you for the link. Yes, that post is generally discussing the same problem that I am having, except that my concern is mainly with the behavior of SYS/BIOS (and the cache settings in the RTSC platform), which are not specifically discussed in that post. I do understand that the L1D and L1P memories are configured as "all cache" after a system reset. I just find it very confusing that the cache settings in the RTSC platform are not put into effect before _auto_init_elf() is executed. From my perspective, when I have a RTSC platform configured as follows...

    ...I find it counterintuitive that I cannot have initialized sections in L1D memory given this "zero cache" platform configuration. I'm hoping that there is a more convenient workaround than prohibiting initialized sections in L1D memory.

    (Just as an aside, the reason we have L1P cache turned off is because we allocate all of our time-critical code directly to that memory.)

    Best regards,
    Dave

  • 0 in reply to Sasha Slijepcevic
    Expert 2021 points

    Good news! I haven't confirmed this experimentally, but according to the SYS/BIOS 6.37.04.32 release notes (software-dl.ti.com/.../bios_6_37_04_32_release_notes.html) the following defect was fixed in that version:

    SDOCM00112780     Modify C66 Cache module to setup/initialize cache as early as possible during boot time    

    I expect that this is exactly the fix that I am looking for.