TDA3MA: TDA3 CSI2 Configuration questions

alexpioner

Part Number: TDA3MA

Hi, all.

The TDA3 TRM says, there is a single CSI2_PHY1 at the CAL_A of the ISS, which is composed of 5 lanes (4 data lanes + 1 clock lane).

1) There is the following configuration register:

What is the meaning of this register for CAL_B module? If I understand right, there is no any PHY at the CAL_B module.

Except two instances there are 2 available offsets (for I=0 and for I=1), so there are 4 different offsets: 0x52012304, 0x52012384, 0x52013304 and 0x52013384

May you check this issue? What are the purposes of this register at each out of four offsets?

2) The TRM has the following note regarding the clock lane:

However, lets see the description of the clock position bitfield at the previously reminded register:

It has the option to place the clock lane at position 4. So what is true?

Best regards,

Alex

over 8 years ago

0 Brijesh Jadav over 8 years ago

TI__Guru**** 504805 points

Hi Alex,

There are two instances of CAL modules in TDA3x, they are exactly same, the difference is, PHY is connected to only CAL-A. CAL-B does not have PHY.
Since both the modules are same, registers are also same. so we see this PHY configuration even for CAL-B.

Regards,
Brijesh

0 Sujith over 8 years ago in reply to Brijesh Jadav

TI__Genius 12455 points

Hi Alex,

Yes lane 4 cannot be used as clock lane. The note is correct and the register description is not accurate.

Regards,
Sujith

0 Alex Bashkov over 8 years ago

TI__Genius 14190 points

Note that the registers are also counting from position 1, while the note above is aligned with pin names, i.e. counts from 0. So actually, you cannot use 0x5 = Clock lane is at position 5 (LANE 4). In general, you cannot use the lane farthest away from the PHY core as a clock, that's just some hardware restriction. Position 5 (LANE 4) happens to be the one with that restriction.

Thanks,
Alex

0 alexpioner over 8 years ago in reply to Alex Bashkov

Prodigy 140 points

Hi, Alex.

Thanks a lot.

Alex

0 alexpioner over 8 years ago in reply to Sujith

Prodigy 140 points

Hi Sujith.

Thanks a lot.

Alex

0 alexpioner over 8 years ago in reply to Brijesh Jadav

Prodigy 140 points

Hi Brijesh.

But what do indexes 0 and 1 mean?

There are two registers for CAL_A and CAL_B, while each register has some additional offset based on index.

Thanks a lot.

Alex

0 Alex Bashkov over 8 years ago in reply to alexpioner

TI__Genius 14190 points

Hi Alex,

These indexes come from ancestor devices that had 2 PHYs. In those devices, each CAL was able to control each PHY, hence the 2 COMPLEXIO_I registers with index = 0 to 1. For the TDA3x case though, we only have 1 CAL configuring the only 1 PHY, so you should be looking for the 0x5201 2304 + (0x80 * I) (where i = 0) physical address only.

Thanks,
Alex

0 alexpioner over 8 years ago in reply to Alex Bashkov

Prodigy 140 points

That's OK.
Thanks

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TDA3MA: TDA3 CSI2 Configuration questions