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66AK2H14: 66AK2H14 EVM DDR3

joe lindula
Mastermind 6940 points

Part Number: 66AK2H14

Hello, I have a question on page 28 of the schematics for the K2EVM-HK Rev. 4. I don't understand why signal SOC_DDR3B_EA15 is tied to NC connect pin M7 on the DDR3 memory. This is done on U43, U40, U42, and U39. 

Thanks,

Joe

  • 0
    TI__Guru**** 161600 points
    Hi Joe,

    Let me check this and I will update.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Guru**** 161600 points
    Hi Joe,

    66AK2Hx deivce has 16 address pins (DDR3BA[0..15]), while the ddr chips used have 15 address pins (A0 - A14). In such cases the Hardware Design Guide for Keystone II devices (www.ti.com/.../sprabv0.pdf) states:
    "All unused DDR3 address pins must be left floating. All unused error correction pins must also be left floating. All remaining control lines must also be left floating when unused. Unused byte lanes must be properly disabled in the appropriate MMR. "

    So in this case, my understanding is that DDR3BA15 can be left floating, which is equivalent to tying it to the NC pin (M7) of the DDR chip. In the case of K2H EVM, the DDR3BA15 is routed to the DDR chip as a future compliance, so that you can replace the DDR chip with one that has 16 address pins.

    Looping the design team to elaborate if necessary.

    Best Regards,
    Yordan