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AM3352: EMU pins not working as GPIO

Matvey Yurevich Vergazov
Prodigy 30 points
Part Number: AM3352


Hi!

I've used EMU1 as GPIO (gpio3_8) in my AM3352 design as an output for a watchdog external IC.

When started to bring up the board software it appeared that EMU1 (EMU0 as well) is not changing values though any other GPIO does.

We've tried to use it from barebox, u-boot and linux - everywhere behavior is the same: EMUx is always up (because of external pull-up), other GPIOs acting fine changing their values according to the commands applied.

Does anyone have any clues?

Thanks in advance for any help.

BR,

Matvey.

  • 0
    TI__Guru**** 393215 points
    Hi,

    Please check Errata Advisories 1.0.3 and 1.0.36.
  • 0 in reply to Biser Gatchev-XID
    Prodigy 30 points
    Hi, Biser!

    Thanks for your reply.

    For the errata:
    1) 1.0.36 EMU0 and EMU1: Terminals Must be Pulled High Before ICEPick Samples
    EMUx pins are pulled up to 3.3V with 4.7k resistors so there shouldn't be problems unless internal capacitance of this pin exceed 20-30pF.

    2) 1.0.3 Debug Subsystem: Internal Inputs Tied-off to the Wrong Value
    We don't use JTAG debug, so there's no need to export any debug messages, does this errata still apply? Or should we change some setting to explicitly turn off exporting of trace messages?

    If exporting trace messages is turned off by default then it seems that these errata advisories don't apply to the case I described.

    Do you have any ideas?

    Thanks.

    BR,
    Matvey
  • 0 in reply to Matvey Yurevich Vergazov
    TI__Guru* 87660 points
    Matvey, what value do you have in the associated pinmux registers when attempting to use them as GPIO? 0x44e109E4 and 0x44E109E8?

    Regards,
    james
  • 0 in reply to JJD
    Prodigy 30 points
    Hi, JJD!

    For the requested registers, their values are:
    barebox@AM335x SOM:/ md -l 0x44e109e4+4
    44e109e4: 00000030 0...
    barebox@AM335x SOM:/ md -l 0x44e109e8+4
    44e109e8: 0000000f ....

    The first one (EMU0) is not used now, so its registers are default I guess.

    Thank for your clue with the correct registers address we've found out that problem is that barebox bootloader and linux kernel somehow don't set GPIO_OD register to allow output capabilities on these pins. When we set it directly in the register - it started working.
    We made an addition to barebox code so that it would set it correctly before booting linux kernel. So now controlling of these GPIO works fine via standard /sys/class/gpio interface.

    What is not clear for me now - what is the correct way to do that?

    We've used these line in DTS file to do that:
    gpio_pins: pinmux_gpio_pins {
    pinctrl-single,pins = <
    0x1e8 (PIN_OUTPUT | MUX_MODE7) /* (B14) EMU1.gpio3[8] */
    >;
    };

    But that alone without our patch didn't help.

    Any advice would be appreciated.
    Thanks.

    BR,
    Matvey