Linux/AM5718: GPMC configuration issue

How do you check the GPMC clock? It's active only during GPMC transactions.

Dear Biser,

Thanks for response.

We are using devmem2 and tried to access the memory at 0x1000000.
root@am57xx-evm:~# devmem2 0x1000000

Thanks,
Suryaprakash Rao G

Which SDK are you using? I'd like to re-create using the same one.

Steve K.

Dear Steve K,

Thank you so much for your response.

I am using the latest SDK 04_03_00_05 and also tried with ti-processor-sdk-linux-am57xx-evm-04.01.00.06.

Write now I am able to observe the Clock , CS, ADV, OE and WE signals with the following configuration and able to read and write into the SRAM. If the GPMC data is 0xFF00, 0x00FF, 0x0FF0,...) then i could read (or) write the data properly.

Facing the problem when we write (or) read with more bits set in the data (i.e 0x3ff, 0x7FF, 0xEEFF, 0xAABB,...). In this scenario we are observing in the chipcscope that ADVWROFFTIME/ADVROFFTIME is completing before the CSONTIME and then memory address appears in the bus. Not able to understand why the Control signals are effecting when we write the data with more bits set.

gpmc_pins: gpmc_pins {
pinctrl-single,pins = <
DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */
DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */
DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */
DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */
DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */
DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */
DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */
DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */
DRA7XX_CORE_IOPAD(0x34C0, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */

DRA7XX_CORE_IOPAD(0x34B4, PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0.gpmc_cs0 */
DRA7XX_CORE_IOPAD(0x34C4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
DRA7XX_CORE_IOPAD(0x34C8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
DRA7XX_CORE_IOPAD(0x34CC, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
DRA7XX_CORE_IOPAD(0x34D0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0.gpmc_ben0 */
DRA7XX_CORE_IOPAD(0x34D4, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0.gpmc_ben1 */
>;
};

sram@0,0 {
reg = <0 0 0x1000000>;
bank-width = <2>;

gpmc,device-width = <2>; /* 16-bit devices */
gpmc,sync-read;
gpmc,sync-write;
gpmc,sync-clk-ps = <11500>; /* Minimum clock period for synchronous mode, in picoseconds */
gpmc,mux-add-data = <2>;

gpmc,cs-on-ns = <12>; /* Assertion time */
gpmc,cs-rd-off-ns = <115>; /* Read deassertion time */
gpmc,cs-wr-off-ns = <115>; /* Write deassertion time */

/* ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3: */
gpmc,adv-on-ns = <12>; /* Assertion time */
gpmc,adv-rd-off-ns = <28>; /* Read deassertion time */
gpmc,adv-wr-off-ns = <28>; /* Write deassertion time */

/* WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: */
gpmc,we-on-ns = <40>; /* Assertion time */
gpmc,we-off-ns = <115>; /* Deassertion time */

/* OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: */
gpmc,oe-on-ns = <28>; /* Assertion time */
gpmc,oe-off-ns = <115>; /* Deassertion time */

/* Access time and cycle time timings (in nanoseconds) corresponding to GPMC_CONFIG5: */
gpmc,access-ns = <92>; /* Start-cycle to first data valid delay */
gpmc,rd-cycle-ns = <115>; /* Total read cycle time */
gpmc,wr-cycle-ns = <115>; /* Total write cycle time */
gpmc,wr-data-mux-bus-ns = <40>; /* */
// gpmc,wr-access-ns = <84>;
};

Thanks,
Suryaprakash Rao. G

Can you dump all your GPMC_CONFIG registers and post them?

Steve K.

Dear Steve K,

Thanks for your response.

Following is the GPMC_CONFIG  registers dump.

======================================

gpmc cs0 endof gpmc_probe_generic_child() :

cs0 GPMC_CS_CONFIG1: 0x28001203

cs0 GPMC_CS_CONFIG2: 0x001f1f04

cs0 GPMC_CS_CONFIG3: 0x00080804

cs0 GPMC_CS_CONFIG4: 0x1f0b1f08

cs0 GPMC_CS_CONFIG5: 0x00191f1f

cs0 GPMC_CS_CONFIG6: 0x800b0000

cs0 GPMC_CS_CONFIG7: 0x00000f41

gpmc cs0 access configuration:

gpmc,mux-add-data = <2>

gpmc,device-width = <1>

gpmc,wait-pin = <0>

gpmc,burst-length = <4>

gpmc,sync-write = <1>

gpmc,gpmc,sync-read = <1>

gpmc cs0 timings configuration:

gpmc,cs-on-ns = <15> /* 12 ns - 15 ns; 4 ticks */

gpmc,cs-rd-off-ns = <116> /* 113 ns - 116 ns; 31 ticks */

gpmc,cs-wr-off-ns = <116> /* 113 ns - 116 ns; 31 ticks */

gpmc,adv-on-ns = <15> /* 12 ns - 15 ns; 4 ticks */

gpmc,adv-rd-off-ns = <30> /* 27 ns - 30 ns; 8 ticks */

gpmc,adv-wr-off-ns = <30> /* 27 ns - 30 ns; 8 ticks */

gpmc,adv-aad-mux-on-ns = <0> /* 0 ns - 0 ns; 0 ticks */

gpmc,adv-aad-mux-rd-off-ns = <0> /* 0 ns - 0 ns; 0 ticks */

gpmc,adv-aad-mux-wr-off-ns = <0> /* 0 ns - 0 ns; 0 ticks */

gpmc,oe-on-ns = <30> /* 27 ns - 30 ns; 8 ticks */

gpmc,oe-off-ns = <116> /* 113 ns - 116 ns; 31 ticks */

gpmc,oe-aad-mux-on-ns = <0> /* 0 ns - 0 ns; 0 ticks */

gpmc,oe-aad-mux-off-ns = <0> /* 0 ns - 0 ns; 0 ticks */

gpmc,we-on-ns = <41> /* 38 ns - 41 ns; 11 ticks */

gpmc,we-off-ns = <116> /* 113 ns - 116 ns; 31 ticks */

gpmc,rd-cycle-ns = <116> /* 113 ns - 116 ns; 31 ticks */

gpmc,wr-cycle-ns = <116> /* 113 ns - 116 ns; 31 ticks */

gpmc,access-ns = <93> /* 91 ns - 93 ns; 25 ticks */

gpmc,page-burst-access-ns = <0> /* 0 ns - 0 ns; 0 ticks */

gpmc,bus-turnaround-ns = <0> /* 0 ns - 0 ns; 0 ticks */

gpmc,cycle2cycle-delay-ns = <0> /* 0 ns - 0 ns; 0 ticks */

gpmc,wait-monitoring-ns = <0> /* 0 ns - 0 ns; 0 ticks */

gpmc,clk-activation-ns = <0> /* 0 ns - 0 ns; 0 ticks */

gpmc,wr-data-mux-bus-ns = <41> /* 38 ns - 41 ns; 11 ticks */

gpmc,wr-access-ns = <0> /* 0 ns - 0 ns; 0 ticks */

============================================

Regards,

Suryaprakash Rao G.

Can you give me more information on the part you are connecting?

Steve K.