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Other Parts Discussed in Thread: DRA714, DRA750, LP8733, DRA722, DRA71
Our processor is DRA714, with 3.02.00.03 SDK version.
In our custom board. we use TPS65917Q1 as our PMIC. As title, which dts file should i use?
P.S. I plan to use dra71-evm.dts, but i can't find any description about PMIC. Only can find TPS65917 description at dra72-evm.dts
Regards,
Shawn
Hi RK,
I already include arch/arm/dts/dra71-evm.dts，and add tps-65917 description at I2C-1 node in our custom dts file, but boot fail, there is no log output after power on.
Here is our uboot dts file =>
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "dra71-evm.dts"
&pcf_gpio_21 {
status = "disabled";
};
&evm_3v3_sd {
gpio = <>;
};
&extcon_usb1 {
id-gpio = <>;
};
&extcon_usb2 {
id-gpio = <>;
};
/ {
chosen {
stdout-path = &uart4;
};
memory {
reg = <0x80000000 0x20000000>; /* 512 MB */
};
};
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins>;
};
&dra7_pmx_core {
uart4_pins: pinmux_uart4_pins {
pinctrl-single,pins = <
0x33C (PIN_INPUT_SLEW | MUX_MODE4) /* uart4_rxd */
0x340 (PIN_INPUT_SLEW | MUX_MODE4) /* uart4_txd */
>;
};
};
/*=================== Add PMIC TPS65917 ==================*/
&i2c1 {
status = "okay";
clock-frequency = <400000>;
tps65917: tps65917@58 {
compatible = "ti,tps65917";
reg = <0x58>;
interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
interrupt-controller;
#interrupt-cells = <2>;
ti,system-power-controller;
tps65917_pmic {
compatible = "ti,tps65917-pmic";
tps65917_regulators: regulators {
smps1_reg: smps1 {
/* VDD_MPU */
regulator-name = "smps1";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps2_reg: smps2 {
/* VDD_CORE */
regulator-name = "smps2";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1060000>;
regulator-boot-on;
regulator-always-on;
};
smps3_reg: smps3 {
/* VDD_GPU IVA DSPEVE */
regulator-name = "smps3";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-boot-on;
regulator-always-on;
};
smps4_reg: smps4 {
/* VDDS1V8 */
regulator-name = "smps4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
smps5_reg: smps5 {
/* VDD_DDR */
regulator-name = "smps5";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: ldo1 {
/* LDO1_OUT --> SDIO */
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-allow-bypass;
};
ldo3_reg: ldo3 {
/* VDDA_1V8_PHY */
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo5_reg: ldo5 {
/* VDDA_1V8_PLL */
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo4_reg: ldo4 {
/* VDDA_3V_USB: VDDA_USBHS33 */
regulator-name = "ldo4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
};
};
tps65917_power_button {
status = "disabled";
compatible = "ti,palmas-pwrbutton";
interrupt-parent = <&tps65917>;
interrupts = <1 IRQ_TYPE_NONE>;
wakeup-source;
ti,palmas-long-press-seconds = <6>;
};
};
};
&mmc1 {
status = "okay";
vmmc-supply = <&evm_3v3_sd>;
vmmc_aux-supply = <&ldo1_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
* is always hardwired.
*/
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
max-frequency = <192000000>;
};
/*=================================================*/
Actually our board schematics is almost the same with dra72-evm at voltage connection, the different part is that smps1_sw & smps2_sw are connect together to serve as one voltage output(VDD_CORE, max=>4.1A), but it is seperate output at dra72-evm. So i am not sure about my dts file setting. Can you help to check that? Thank you.
Regards,
Shawn
Hi Shawn,
I see that you added new child node for PMIC under i2C1 but you also need to remove other child nodes (lp8733: lp8733@60 and lp8732: lp8732@61 ) form the parent node if they don't exist.
Also, If your board is similar to dra72-evm then better use dra71-evm.dts as a base file.
You also need to update following data structures in board/ti/dra7xx/evm.c.
struct vcores_data dra722_volts = {};
for example, in default data structure , mpu is set to use SMPS1 (change this to reflect connections on your board), similarly for other cores.
.mpu.addr = TPS65917_REG_ADDR_SMPS1,
.mpu.pmic = &tps659038, (This should be okay because /* The TPS659038 and TPS65917 are software-compatible, use common struct */)
Also modify vcores_update() in the same file to return the modified data structure for your board.
If you still can't get it working then please share your schematics (at least power / voltage supply connections part).
Regards,
RK
Hi RK,
Update the latest situation.
I can see some log info at u-boot phase, but still stuck at u-boot. Here is the log =>
U-Boot SPL 2016.05-g35dae4d-dirty (May 24 2018 - 15:42:23) DRA722-GP ES2.0 ti_i2c_eeprom_init failed 1 964 -> optimize_vcore_voltage:efuse 0x4a003b20 bits=16 Vnom=964, using efuse value 964 964 1064 -> optimize_vcore_voltage:efuse 0x4a0025f4 bits=16 Vnom=1064, using efuse value 1064 1064 0 -> 0 979 -> optimize_vcore_voltage:efuse 0x4a003b08 bits=16 Vnom=979, using efuse value 979 979 0 -> 0 0 -> 0 cor: 1064 do_scale_vcore: volt - 1064 offset_code - 0x3f IODELAY: IO delay recalibration successfully completed mpu: 964 do_scale_vcore: volt - 964 offset_code - 0x35 mm: 0 gpu: 979 do_scale_vcore: volt - 979 offset_code - 0x36 eve: 0 iva: 0 setup_dplls core Dpll already locked with idealnominal opp valuesCore DPLL configured per Dpll already locked with idealnominal opp valu�sPER DPLL locked mpu Dpll already locked with idealnominal opp valuesMPU DPLL locked usb Dpll already locked with idealnominal opp valuesBypassing DPLL failed 4a008180 ddr Dpll already locked with idealnominal opp values gmac Dpll already locked with idealnominal opp values>>sdram_init() in_sdram = 0 >>do_sdram_init() 4c000000 MII 0 power strap setting(Pull low COL,CRS *****ID_CODE is: 0x7220200 HW leveling success <<do_sdram_init() 4c000000 SDRAM: identified size not same as expected size identified: 20000000 expected: 40000000 enter here-2 <<sdram_init() (spl.c).....board_init_r() done >>spl:board_init_r() TLB table from c0ffb000 to c1000000 dram_bank_mmu_setup: bank: 0 dram_bank_mmu_setup: bank: 1 using memory 0x80a80000-0x81a80000 for malloc() spl_init() ***spl_init() done*** ***board_init_r() step-1*** ***spl_board_init() start*** ***spl_board_init() step-1*** ***spl_board_init() step-2*** ***spl_board_init() step-3*** ***spl_board_init() step-4*** ***spl_board_init() step-5*** ***spl_board_init() step-6*** ***spl_board_init() step-7*** ***board_init() start*** ***spl_mmc_init() start*** ***spl_mmc_init() step-1*** ***spl_mmc_init() step-2*** ***spl_mmc_init() step-3*** ***mmc_init() start*** ***mmc_init() step-1*** ***mmc_init() step-2*** ***mmc_start_init() start*** ***mmc_start_init() step-1*** ***mmc_start_init() step-2*** ***omap_hsmmc_init_setup() start*** ***mmc_board_init() start*** ***mmc_board_init() step-3*** ***mmc_board_init() step-4*** ***vmmc_pbias_config() start***
What i modify list below:
1. dts file use dra72-evm.dts. Here is dts file =>
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
//#include "dra7-evm.dts"
//#include "dra71-evm.dts" //for MAN2020 512M (Dra714)
#include "dra72-evm.dts"
&pcf_gpio_21 {
status = "disabled";
};
&evm_3v3_sd {
gpio = <>;
};
&extcon_usb1 {
id-gpio = <>;
};
&extcon_usb2 {
id-gpio = <>;
};
/ {
chosen {
stdout-path = &uart4;
};
memory {
reg = <0x80000000 0x20000000>; /* 512 MB */
};
};
&uart4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins>;
};
&dra7_pmx_core {
uart4_pins: pinmux_uart4_pins {
pinctrl-single,pins = <
0x33C (PIN_INPUT_SLEW | MUX_MODE4) /* uart4_rxd */
0x340 (PIN_INPUT_SLEW | MUX_MODE4) /* uart4_txd */
>;
};
};
&qspi {
status = "okay";
spi-max-frequency = <64000000>;
m25p80@0 {
compatible = "s25fl256s1","spi-flash";
spi-max-frequency = <76800000>;
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
#address-cells = <1>;
#size-cells = <1>;
/* MTD partition table.
* The ROM checks the first four physical blocks
* for a valid file to boot and the flash here is
* 64KiB block size.
*/
/*
partition@0 {
label = "QSPI.SPL";
reg = <0x00000000 0x000010000>;
};
partition@1 {
label = "QSPI.SPL.backup1";
reg = <0x00010000 0x00010000>;
};
partition@2 {
label = "QSPI.SPL.backup2";
reg = <0x00020000 0x00010000>;
};
partition@3 {
label = "QSPI.SPL.backup3";
reg = <0x00030000 0x00010000>;
};
*/
partition@0 {
label = "QSPI.MLO";
reg = <0x00000000 0x000040000>;
};
partition@1 {
label = "QSPI.u-boot";
reg = <0x00040000 0x00100000>;
};
partition@2 {
label = "QSPI.DRA7-evm.dtb";
reg = <0x00140000 0x00080000>;
};
partition@3 {
label = "QSPI.u-boot-env";
reg = <0x001c0000 0x00010000>;
};
partition@4 {
label = "QSPI.u-boot-env.backup1";
reg = <0x001d0000 0x0010000>;
};
partition@5 {
label = "QSPI.uImage";
reg = <0x001e0000 0x0800000>;
};
partition@6 {
label = "QSPI.IPU-exe";
reg = <0x009e0000 0x01620000>;
};
};
};
#if 0
/*=================== Add PMIC TPS65917 ==================*/
&i2c1 {
status = "okay";
clock-frequency = <400000>;
tps65917: tps65917@58 {
compatible = "ti,tps65917";
reg = <0x58>;
//interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
interrupt-controller;
#interrupt-cells = <2>;
ti,system-power-controller;
interrupts = <>; /* disable interrupt */
tps65917_pmic {
compatible = "ti,tps65917-pmic";
tps65917_regulators: regulators {
smps1_reg: smps1 {
/* VDD_MPU */
regulator-name = "smps1";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-always-on;
regulator-boot-on;
};
smps2_reg: smps2 {
/* VDD_CORE */
regulator-name = "smps2";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1060000>;
regulator-boot-on;
regulator-always-on;
};
smps3_reg: smps3 {
/* VDD_GPU IVA DSPEVE */
regulator-name = "smps3";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
regulator-boot-on;
regulator-always-on;
};
smps4_reg: smps4 {
/* VDDS1V8 */
regulator-name = "smps4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
smps5_reg: smps5 {
/* VDD_DDR */
regulator-name = "smps5";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: ldo1 {
/* LDO1_OUT --> SDIO */
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-allow-bypass;
};
ldo3_reg: ldo3 {
/* VDDA_1V8_PHY */
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo5_reg: ldo5 {
/* VDDA_1V8_PLL */
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo4_reg: ldo4 {
/* VDDA_3V_USB: VDDA_USBHS33 */
regulator-name = "ldo4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
};
};
tps65917_power_button {
status = "disabled";
compatible = "ti,palmas-pwrbutton";
interrupt-parent = <&tps65917>;
interrupts = <1 IRQ_TYPE_NONE>;
wakeup-source;
ti,palmas-long-press-seconds = <6>;
};
};
};
&mmc1 {
status = "okay";
vmmc-supply = <&evm_3v3_sd>;
vmmc_aux-supply = <&ldo1_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
* is always hardwired.
*/
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
max-frequency = <192000000>;
};
#endif
/*=================================================*/
#if 0
&mmc3 {
status = "okay";
vmmc-supply = <&evm_3v3_sd>;
vmmc_aux-supply = <&ldo1_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
* is always hardwired.
*/
//cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
max-frequency = <64000000>;
};
#endif
2. at vcore_update(), i force *omap_vcores to be dra722_volts. Here is evm.c =>
/*
* (C) Copyright 2013
* Texas Instruments Incorporated, <www.ti.com>
*
* Lokesh Vutla <lokeshvutla@ti.com>
*
* Based on previous work by:
* Aneesh V <aneesh@ti.com>
* Steve Sakoman <steve@sakoman.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <palmas.h>
#include <sata.h>
#include <linux/string.h>
#include <asm/gpio.h>
#include <usb.h>
#include <fdt_support.h>
#include <linux/usb/gadget.h>
#include <asm/omap_common.h>
#include <asm/omap_sec_common.h>
#include <asm/arch/gpio.h>
#include <asm/arch/dra7xx_iodelay.h>
#include <asm/emif.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sata.h>
#include <environment.h>
#include <dwc3-uboot.h>
#include <dwc3-omap-uboot.h>
#include <i2c.h>
#include <ti-usb-phy-uboot.h>
#include <miiphy.h>
#include <spl.h>
#include "mux_data.h"
#include "../common/board_detect.h"
#define board_is_dra74x_evm() board_ti_is("5777xCPU")
#define board_is_dra72x_evm() board_ti_is("DRA72x-T")
#define board_is_dra71x_evm() board_ti_is("DRA79x,D")
#define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \
(strncmp("H", board_ti_get_rev(), 1) <= 0))
#define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \
(strncmp("C", board_ti_get_rev(), 1) <= 0))
//#define board_ti_get_emif_size() board_ti_get_emif1_size() + \
// board_ti_get_emif2_size()
//#define board_ti_get_emif_size() 536870912
#define ENABLE_CAX50_SUPPORT
#define DDR_512_VARIANT
//#define DDR_2G_VARIANT
//#define DDR_3G_VARIANT
//#define DRA71_FORCE
#ifdef CONFIG_DRIVER_TI_CPSW
#include <cpsw.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* GPIO 7_11 */
#define GPIO_DDR_VTT_EN 203
#define SYSINFO_BOARD_NAME_MAX_LEN 37
/* I2C I/O Expander */
#define SW5_PCF8575_ADDR 0x21
#define SW5_PCF8575_I2C_BUS_NUM 0
const struct omap_sysinfo sysinfo = {
"Board: UNKNOWN(DRA7 EVM) REV UNKNOWN\n"
};
/* HW ID */
#define HW_ID_2 37 /* GPIO2_5 */
#define HW_ID_1 38 /* GPIO2_6 */
#define HW_ID_0 39 /* GPIO2_7 */
unsigned char get_Module_HW_ID_Version(void);
unsigned long board_ti_get_emif_size(void);
#ifdef ENABLE_CAX50_SUPPORT
const struct emif_regs emif1_ddr3_532_mhz_1cs_512MBx32 = {
.sdram_config_init = 0x61856332,
.sdram_config = 0x61856332,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x30BF7FDA,
.sdram_tim3 = 0x427F8BA8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct emif_regs emif1_ddr3_532_mhz_1cs_256MB = {
.sdram_config_init = 0x618562b2,
.sdram_config = 0x618562b2,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x30BF7FDA,
.sdram_tim3 = 0x427F8BA8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct emif_regs emif2_ddr3_532_mhz_1cs_512MBx32 = {
.sdram_config_init = 0x61856332,
.sdram_config = 0x61856332,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x30BF7FDA,
.sdram_tim3 = 0x427F8BA8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct emif_regs emif2_ddr3_532_mhz_1cs_256MB = {
.sdram_config_init = 0x618562b2,
.sdram_config = 0x618562b2,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x30BF7FDA,
.sdram_tim3 = 0x427F8BA8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
#endif
const struct emif_regs emif1_ddr3_532_mhz_1cs_256MBx2 = {
.sdram_config_init = 0x61811b32,
.sdram_config = 0x61811b32,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x2000081e,
.ref_ctrl_final = 0x0000081e,
.sdram_tim1 = 0xceef266c,
.sdram_tim2 = 0x728f7fe3,
.sdram_tim3 = 0x029f88a8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0824400a,
.emif_ddr_phy_ctlr_1 = 0x0e24400a,
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00850085,
.emif_ddr_ext_phy_ctrl_3 = 0x00850085,
.emif_ddr_ext_phy_ctrl_4 = 0x00850085,
.emif_ddr_ext_phy_ctrl_5 = 0x00850085,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct emif_regs emif2_ddr3_532_mhz_1cs_256MBx2 = {
.sdram_config_init = 0x62811AB2,
.sdram_config = 0x62811AB2,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x305A7FDA,
.sdram_tim3 = 0x407F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0824400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct emif_regs emif1_ddr3_532_mhz_1cs_512MBx4 = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x407F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct emif_regs emif2_ddr3_532_mhz_1cs_512MBx4 = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x407F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct emif_regs emif1_ddr3_532_mhz_1cs_1GBx2_512MBx2 = {
.sdram_config_init = 0x61851BB2,
.sdram_config = 0x61851BB2,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x30BF7FDA,
.sdram_tim3 = 0x407F8BA8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct emif_regs emif2_ddr3_532_mhz_1cs_1GBx2_512MBx2 = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x407F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
#if 1 /* Bryant Modify (CAX50-512 MB)*/
const struct emif_regs emif1_ddr3_532_mhz_1cs = {
.sdram_config_init = 0x61856332,
.sdram_config = 0x61856332,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x30BF7FDA,
.sdram_tim3 = 0x427F8BA8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
#else
static const struct emif_regs emif1_ddr3_532_mhz_1cs = {
.sdram_config_init = 0x61851ab2,
.sdram_config = 0x61851ab2,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x427F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
#endif
static const struct emif_regs emif2_ddr3_532_mhz_1cs = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x427F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
.sdram_config_init = 0x61862B32,
.sdram_config = 0x61862B32,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x0000514C,
.ref_ctrl_final = 0x0000144A,
.sdram_tim1 = 0xD113781C,
.sdram_tim2 = 0x30717FE3,
.sdram_tim3 = 0x409F86A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400D,
.emif_ddr_phy_ctlr_1 = 0x0E24400D,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00A400A4,
.emif_ddr_ext_phy_ctrl_3 = 0x00A900A9,
.emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es2 = {
.sdram_config_init = 0x61862BB2,
.sdram_config = 0x61862BB2,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x0000514D,
.ref_ctrl_final = 0x0000144A,
.sdram_tim1 = 0xD1137824,
.sdram_tim2 = 0x30B37FE3,
.sdram_tim3 = 0x409F8AD8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0824400E,
.emif_ddr_phy_ctlr_1 = 0x0E24400E,
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x006B009F,
.emif_ddr_ext_phy_ctrl_3 = 0x006B00A2,
.emif_ddr_ext_phy_ctrl_4 = 0x006B00A8,
.emif_ddr_ext_phy_ctrl_5 = 0x006B00A8,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
.sdram_config_init = 0x61851ab2,
.sdram_config = 0x61851ab2,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x30BF7FDA,
.sdram_tim3 = 0x427F8BA8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
.sdram_config_init = 0x61851B32,
.sdram_config = 0x61851B32,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x427F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400B,
.emif_ddr_phy_ctlr_1 = 0x0E24400B,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305
};
void Info_by_GPIO(int pulse_num)
{
#define Boot_Info_0 4 //gpio1_4 (1-1) x 32 + 4
gpio_request(Boot_Info_0,"Boot info");
for(int x=0;x<pulse_num; x++)
{
gpio_direction_output(Boot_Info_0, 0);
__udelay(1000);
gpio_direction_output(Boot_Info_0, 1);
__udelay(1000);
}
}
#if 1 /*Add By Bryant*/
void MII2MDI_PWR_STRIP(void)
{
#define MII_0_CONFIG_0 143 //gpio5_15 (5-1) x 32 +15
#define MII_0_CONFIG_1 150 //gpio5_22
gpio_request(MII_0_CONFIG_0,"STRAP_CONFIG_0");
gpio_request(MII_0_CONFIG_1,"STRAP_CONFIG_1");
gpio_direction_output(MII_0_CONFIG_0, 0);
gpio_direction_output(MII_0_CONFIG_1, 0);
__udelay(100000);
printf("\nMII 0 power strap setting(Pull low COL,CRS");
printf("\n*****ID_CODE is: 0x%x\n", omap_revision());
}
unsigned char get_Module_HW_ID_Version(void)
{
unsigned char HW_ID = 0;
gpio_request(HW_ID_2,"HW_ID_2");
gpio_request(HW_ID_1,"HW_ID_1");
gpio_request(HW_ID_0,"HW_ID_0");
gpio_direction_input( HW_ID_2 );
gpio_direction_input( HW_ID_1 );
gpio_direction_input( HW_ID_0 );
HW_ID += ( 4 * gpio_get_value( HW_ID_2 ) );
HW_ID += ( 2 * gpio_get_value( HW_ID_1 ) );
HW_ID += ( 1 * gpio_get_value( HW_ID_0 ) );
return HW_ID;
}
unsigned long board_ti_get_emif_size(void)
{
unsigned long Size = 0 ;
switch ( get_Module_HW_ID_Version() )
{
case 0: Size = ( 2147483648UL + 1 ); /* 2GB */
break;
case 1: Size = ( 536870912UL + 1 ); /* 512MB */
break;
case 7: Size = ( 3221225472UL + 1); /* 3GB */
break;
#ifdef ENABLE_CAX50_SUPPORT
//below for CAX50 old config
case 3: Size = (268435456UL + 1); /* 256MB */
break;
case 5: Size = (536870912UL + 1); /* 512MB */
break;
#endif
default : Size = (268435456UL + 1); /* 256MB */
break;
}/* end switch */
//======== sean =======================================
// Size = (268435456UL + 1); /* 256MB */
#ifdef DDR_512_VARIANT
Size = ( 536870912UL + 1 ); /* 512MB */
#endif
#ifdef DDR_2G_VARIANT
Size = ( 2147483648UL + 1 ); /* 2GB */
#endif
#ifdef DDR_3G_VARIANT
Size = ( 3221225472UL + 1); /* 3GB */
#endif
//=====================================================
return Size;
}
#endif
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
{
u64 ram_size;
//ram_size = board_ti_get_emif_size();
switch (omap_revision()) {
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA752_ES2_0:
switch (emif_nr) {
case 1:
switch ( get_Module_HW_ID_Version() )
{
case 0: /* 2GB */
*regs = &emif1_ddr3_532_mhz_1cs_512MBx4;
break;
case 1: /* 512MB */
*regs = &emif1_ddr3_532_mhz_1cs_256MBx2;
break;
case 7: /* 3GB */
*regs = &emif1_ddr3_532_mhz_1cs_1GBx2_512MBx2;
break;
#ifdef ENABLE_CAX50_SUPPORT
case 5: /* 512MB */
//setenv("512MB", "1");
*regs = &emif1_ddr3_532_mhz_1cs_512MBx32;
break;
case 3: /* 256MB */
*regs = &emif1_ddr3_532_mhz_1cs_256MB;
break;
#endif
default :
*regs = &emif1_ddr3_532_mhz_1cs_256MB;
break;
}
break;
case 2:
switch ( get_Module_HW_ID_Version() )
{
case 0: /* 2GB */
*regs = &emif2_ddr3_532_mhz_1cs_512MBx4;
break;
case 7: /* 3GB */
*regs = &emif2_ddr3_532_mhz_1cs_1GBx2_512MBx2;
break;
#ifdef ENABLE_CAX50_SUPPORT
case 5: /* 512MB */
*regs = &emif2_ddr3_532_mhz_1cs_512MBx32;
break;
case 3: /* 256MB */
*regs = &emif2_ddr3_532_mhz_1cs_256MB;
break;
#endif
default :
*regs = &emif2_ddr3_532_mhz_1cs_256MB;
break;
}
break;
}
break;
case DRA722_ES1_0:
case DRA722_ES2_0:
if (ram_size < CONFIG_MAX_MEM_MAPPED)
*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
else
*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
break;
default:
*regs = &emif1_ddr3_532_mhz_1cs;
break;
}
//===========sean=========================================================
switch (emif_nr) {
#if 0
case 1: /* 256MB */
*regs = &emif1_ddr3_532_mhz_1cs_256MB;
break;
case 2:
*regs = &emif2_ddr3_532_mhz_1cs_256MB;
break;
#endif
#ifdef DDR_512_VARIANT
case 1: /* 512MB */
*regs = &emif1_ddr3_532_mhz_1cs_256MBx2;
break;
case 2: /* do nothing */
break;
#endif
#ifdef DDR_2G_VARIANT
case 1: /* 2GB */
*regs = &emif1_ddr3_532_mhz_1cs_512MBx4;
break;
case 2: /* 2GB */
*regs = &emif2_ddr3_532_mhz_1cs_512MBx4;
break;
#endif
#ifdef DDR_3G_VARIANT
case 1: /* 3GB */
*regs = &emif1_ddr3_532_mhz_1cs_1GBx2_512MBx2;
break;
case 2: /* 3GB */
*regs = &emif2_ddr3_532_mhz_1cs_1GBx2_512MBx2;
break;
#endif
}
//============================================================================
#if 1 /*Add By Bryant*/
MII2MDI_PWR_STRIP();
#endif
}
static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x80640300,
.dmm_lisa_map_2 = 0xC0500220,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
//Add By Bryant
static const struct dmm_lisa_map_regs lisa_map_dra7_256MB = {
.dmm_lisa_map_0 = 0x00000000,
.dmm_lisa_map_1 = 0x00000000,
.dmm_lisa_map_2 = 0x80400100,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
static const struct dmm_lisa_map_regs lisa_map_dra7_512MB = {
.dmm_lisa_map_0 = 0x00000000,
.dmm_lisa_map_1 = 0x00000000,
.dmm_lisa_map_2 = 0x80500100,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x80600100,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x80740300,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
static const struct dmm_lisa_map_regs lisa_map_dra7_MAN2020_512MB = {
.dmm_lisa_map_0 = 0x80600100,
.dmm_lisa_map_1 = 0xC0000120,
.dmm_lisa_map_2 = 0x00000000,
.dmm_lisa_map_3 = 0x00000000,
.is_ma_present = 0x1
};
static const struct dmm_lisa_map_regs lisa_map_dra7_MAN2020_2GB = {
.dmm_lisa_map_0 = 0x00000000,
.dmm_lisa_map_1 = 0x80640300,
.dmm_lisa_map_2 = 0xC0600220,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
static const struct dmm_lisa_map_regs lisa_map_dra7_MAN2020_3GB = {
.dmm_lisa_map_0 = 0x00000000,
.dmm_lisa_map_1 = 0x80740300,
.dmm_lisa_map_2 = 0xC0600220,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
/*
* DRA722 EVM EMIF1 2GB CONFIGURATION
* EMIF1 4 devices of 512Mb x 8 Micron
*/
const struct dmm_lisa_map_regs lisa_map_2G_x_4 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
.dmm_lisa_map_2 = 0x80700100,
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
u64 ram_size;
ram_size = board_ti_get_emif_size();
switch (omap_revision()) {
case DRA752_ES1_0:
case DRA752_ES1_1:
case DRA752_ES2_0:
switch ( get_Module_HW_ID_Version() )
{
case 0: /* 2GB */
*dmm_lisa_regs = &lisa_map_dra7_MAN2020_2GB;
break;
case 1: /* 512MB */
*dmm_lisa_regs = &lisa_map_dra7_MAN2020_512MB;
break;
case 7: /* 3GB */
*dmm_lisa_regs = &lisa_map_dra7_MAN2020_3GB;
break;
#ifdef ENABLE_CAX50_SUPPORT
case 5: /* 512MB */
*dmm_lisa_regs = &lisa_map_dra7_512MB;
break;
case 3: /* 256MB */
*dmm_lisa_regs = &lisa_map_dra7_256MB;
break;
#endif
default :
*dmm_lisa_regs = &lisa_map_dra7_256MB;
break;
}
break;
case DRA722_ES1_0:
case DRA722_ES2_0:
default:
if (ram_size < CONFIG_MAX_MEM_MAPPED)
*dmm_lisa_regs = &lisa_map_2G_x_2;
else
*dmm_lisa_regs = &lisa_map_2G_x_4;
break;
}
//============= Sean =======================
//*dmm_lisa_regs = &lisa_map_dra7_256MB;
#ifdef DDR_512_VARIANT
*dmm_lisa_regs = &lisa_map_dra7_MAN2020_512MB;
#endif
#ifdef DDR_2G_VARIANT
*dmm_lisa_regs = &lisa_map_dra7_MAN2020_2GB;
#endif
#ifdef DDR_3G_VARIANT
*dmm_lisa_regs = &lisa_map_dra7_MAN2020_3GB;
#endif
//==========================================
}
struct vcores_data dra752_volts = {
.mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
.mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS659038_REG_ADDR_SMPS12,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
.eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
.eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
.eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
.eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
.eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
.gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
.gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
.gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
.core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
.core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS659038_REG_ADDR_SMPS7,
.core.pmic = &tps659038,
.iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
.iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
.iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
.iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
.iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
.iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS8,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
struct vcores_data dra722_volts = {
.mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
.mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = TPS65917_REG_ADDR_SMPS1,
.mpu.pmic = &tps659038,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
.core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
.core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = TPS65917_REG_ADDR_SMPS2,
.core.pmic = &tps659038,
/*
* The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
* designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
*/
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
.gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
.gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
.gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS65917_REG_ADDR_SMPS3,
.gpu.pmic = &tps659038,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
.eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
.eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
.eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
.eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
.eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS65917_REG_ADDR_SMPS3,
.eve.pmic = &tps659038,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
.iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
.iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
.iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
.iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
.iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
.iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS65917_REG_ADDR_SMPS3,
.iva.pmic = &tps659038,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
struct vcores_data dra718_volts = {
/*
* In the case of dra71x GPU MPU and CORE
* are all powered up by BUCK0 of LP873X PMIC
*/
.mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
.mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.mpu.addr = LP873X_REG_ADDR_BUCK0,
.mpu.pmic = &lp8733,
.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
.core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
.core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.core.addr = LP873X_REG_ADDR_BUCK0,
.core.pmic = &lp8733,
.gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
.gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = LP873X_REG_ADDR_BUCK0,
.gpu.pmic = &lp8733,
.gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
/*
* The DSPEVE and IVA rails are grouped on DRA71x-evm
* and are powered by BUCK1 of LP873X PMIC
*/
.eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
.eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = LP873X_REG_ADDR_BUCK1,
.eve.pmic = &lp8733,
.eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
.iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
.iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = LP873X_REG_ADDR_BUCK1,
.iva.pmic = &lp8733,
.iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
int get_voltrail_opp(int rail_offset)
{
int opp;
/*
* DRA71x supports only OPP_NOM.
*/
if (board_is_dra71x_evm())
return OPP_NOM;
switch (rail_offset) {
case VOLT_MPU:
opp = DRA7_MPU_OPP;
break;
case VOLT_CORE:
opp = DRA7_CORE_OPP;
break;
case VOLT_GPU:
opp = DRA7_GPU_OPP;
break;
case VOLT_EVE:
opp = DRA7_DSPEVE_OPP;
break;
case VOLT_IVA:
opp = DRA7_IVA_OPP;
break;
default:
opp = OPP_NOM;
}
return opp;
}
/**
* @brief board_init
*
* @return 0
*/
int board_init(void)
{
int err = 0;
debug("\n***board_init() start***\n");
#ifndef CONFIG_SPL_DFU_SUPPORT
#ifdef CONFIG_SPL_ENV_SUPPORT
#ifdef CONFIG_ENV_IS_IN_MMC
struct mmc *mmc;
//spl_mmc_init(&mmc, UINT_MAX);
err = spl_mmc_init(&mmc, UINT_MAX);
#endif
/*
env_init();
env_relocate_spec();
omap_die_id_serial();
*/
debug("\n***board_init() step-1***\n");
if(!err) {
env_init();
env_relocate_spec();
omap_die_id_serial();
}
#endif
#endif
debug("\n***board_init() step-2***\n");
gpmc_init();
gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
debug("\n***board_init() done***\n");
return 0;
}
void dram_init_banksize(void)
{
u64 ram_size;
ram_size = board_ti_get_emif_size();
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = get_effective_memsize();
if (ram_size > CONFIG_MAX_MEM_MAPPED) {
gd->bd->bi_dram[1].start = 0x200000000;
gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED;
}
}
int board_late_init(void)
{
int HW_ID = 0;
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
char *name = "unknown";
if (is_dra72x()) {
if (board_is_dra72x_revc_or_later())
name = "dra72x-revc";
else if (board_is_dra71x_evm())
name = "dra71x";
else
name = "dra72x";
} else {
name = "dra7xx";
#ifdef CONFIG_TARGET_MAN2020_ADAPTER
name = "MAN2020_ADAPTER";
#endif
}
set_board_info_env(name);
/*
* Default FIT boot on HS devices. Non FIT images are not allowed
* on HS devices.
*/
if (get_device_type() == HS_DEVICE)
setenv("boot_fit", "1");
HW_ID = get_Module_HW_ID_Version();
if(HW_ID == 0)
setenv("MAN2020", "2");
else if(HW_ID == 1)
setenv("MAN2020", "1");
else if(HW_ID == 7)
setenv("MAN2020", "3");
#ifdef ENABLE_CAX50_SUPPORT
else if(HW_ID == 5)
setenv("MAN2020", "1");
#endif
omap_die_id_serial();
omap_set_fastboot_vars();
#endif
return 0;
}
#ifdef CONFIG_SPL_BUILD
void do_board_detect(void)
{
int rc;
rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
CONFIG_EEPROM_CHIP_ADDRESS);
if (rc)
printf("ti_i2c_eeprom_init failed %d\n", rc);
}
#else
void do_board_detect(void)
{
char *bname = NULL;
int rc;
rc = ti_i2c_eeprom_dra7_get(CONFIG_EEPROM_BUS_ADDRESS,
CONFIG_EEPROM_CHIP_ADDRESS);
if (rc)
printf("ti_i2c_eeprom_init failed %d\n", rc);
if (board_is_dra74x_evm()) {
bname = "DRA74x EVM";
} else if (board_is_dra72x_evm()) {
bname = "DRA72x EVM";
} else if (board_is_dra71x_evm()) {
bname = "DRA71x EVM";
} else {
/* If EEPROM is not populated */
if (is_dra72x())
bname = "DRA72x EVM";
else
bname = "DRA74x EVM";
}
if (bname)
snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
"Board: %s REV %s\n", bname, board_ti_get_rev());
}
#endif /* CONFIG_SPL_BUILD */
void vcores_update(void)
{
if (board_is_dra74x_evm()) {
*omap_vcores = &dra752_volts;
} else if (board_is_dra72x_evm()) {
*omap_vcores = &dra722_volts;
} else if (board_is_dra71x_evm()) {
*omap_vcores = &dra718_volts;
} else {
/* If EEPROM is not populated */
if (is_dra72x())
*omap_vcores = &dra722_volts;
else
*omap_vcores = &dra752_volts;
}
#ifdef DDR_512_VARIANT
*omap_vcores = &dra722_volts;
#endif
}
void set_muxconf_regs(void)
{
do_set_mux32((*ctrl)->control_padconf_core_base,
early_padconf, ARRAY_SIZE(early_padconf));
}
#if defined(CONFIG_NAND)
int nand_sw_detect(void)
{
#if 0
int rc, alen;
uchar data[2];
alen = 1;
rc = i2c_set_bus_num(SW5_PCF8575_I2C_BUS_NUM);
if (rc)
return -1;
rc = i2c_probe(SW5_PCF8575_ADDR);
if (rc < 0)
return -1;
rc = ti_i2c_set_alen(SW5_PCF8575_I2C_BUS_NUM, SW5_PCF8575_ADDR, alen);
if (rc < 0)
return -1;
i2c_read(SW5_PCF8575_ADDR, 0x00, alen, (uint8_t *)&data, sizeof(data));
/* We are only interested in P10 and P11 on PCF8575 which is equal to
* bits 8 and 9.
*/
data[1] = data[1] & 0x3;
/* Insure only P11 is set and P10 is cleared. This insures only
* NAND (P10) is configured and not NOR (P11) which are both low
* true signals. NAND and NOR settings should not be enabled at
* the same time.
*/
if (data[1] == 0x2)
return 0;
#endif
return -1;
}
#else
int nand_sw_detect(void)
{
return -1;
}
#endif
#ifdef CONFIG_IODELAY_RECALIBRATION
void recalibrate_iodelay(void)
{
struct pad_conf_entry const *pads, *delta_pads = NULL;
struct iodelay_cfg_entry const *iodelay;
int npads, niodelays, delta_npads = 0;
int ret;
switch (omap_revision()) {
case DRA722_ES1_0:
case DRA722_ES2_0:
pads = dra72x_core_padconf_array_common;
npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
if (board_is_dra71x_evm()) {
pads = dra71x_core_padconf_array;
npads = ARRAY_SIZE(dra71x_core_padconf_array);
iodelay = dra71_iodelay_cfg_array;
niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
} else if (board_is_dra72x_revc_or_later()) {
delta_pads = dra72x_rgmii_padconf_array_revc;
delta_npads =
ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
iodelay = dra72_iodelay_cfg_array_revc;
niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
} else {
delta_pads = dra72x_rgmii_padconf_array_revb;
delta_npads =
ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
iodelay = dra72_iodelay_cfg_array_revb;
niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
}
break;
case DRA752_ES1_0:
case DRA752_ES1_1:
pads = dra74x_core_padconf_array;
npads = ARRAY_SIZE(dra74x_core_padconf_array);
iodelay = dra742_es1_1_iodelay_cfg_array;
niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
/* If SW5 on the EVM is set to enable NAND then overwrite
* the pins used by VOUT3 with NAND.
*/
//if (!nand_sw_detect()) {
delta_pads = dra74x_nand_padconf_array;
delta_npads =
ARRAY_SIZE(dra74x_nand_padconf_array);
//}
break;
default:
case DRA752_ES2_0:
pads = dra74x_core_padconf_array;
npads = ARRAY_SIZE(dra74x_core_padconf_array);
iodelay = dra742_es2_0_iodelay_cfg_array;
niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
/* Setup port1 and port2 for rgmii with 'no-id' mode */
clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
RGMII1_ID_MODE_N_MASK);
/* If SW5 on the EVM is set to enable NAND then overwrite
* the pins used by VOUT3 with NAND.
*/
//if (!nand_sw_detect()) {
delta_pads = dra74x_nand_padconf_array;
delta_npads =
ARRAY_SIZE(dra74x_nand_padconf_array);
//}
break;
}
#ifdef DDR_512_VARIANT
/* below for dra71x pad setting */
#if 1
pads = dra71x_core_padconf_array;
npads = ARRAY_SIZE(dra71x_core_padconf_array);
iodelay = dra71_iodelay_cfg_array;
niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
#endif
/*----------------------------------------------*/
#endif
/* Setup I/O isolation */
ret = __recalibrate_iodelay_start();
if (ret)
goto err;
/* Do the muxing here */
do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);
/* Now do the weird minor deltas that should be safe */
if (delta_npads)
do_set_mux32((*ctrl)->control_padconf_core_base,
delta_pads, delta_npads);
/* Setup IOdelay configuration */
ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
err:
/* Closeup.. remove isolation */
__recalibrate_iodelay_end(ret);
}
#endif
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
int board_mmc_init(bd_t *bis)
{
omap_mmc_init(0, 0, 0, -1, -1);
omap_mmc_init(1, 0, 0, -1, -1);
return 0;
}
#endif
#ifdef CONFIG_OMAP_HSMMC
int platform_fixup_disable_uhs_mode(void)
{
return omap_revision() == DRA752_ES1_1;
}
#endif
#ifdef CONFIG_USB_DWC3
static struct dwc3_device usb_otg_ss1 = {
.maximum_speed = USB_SPEED_SUPER,
.base = DRA7_USB_OTG_SS1_BASE,
.tx_fifo_resize = false,
.index = 0,
};
static struct dwc3_omap_device usb_otg_ss1_glue = {
.base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE,
.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
.index = 0,
};
static struct ti_usb_phy_device usb_phy1_device = {
.pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL,
.usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER,
.usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER,
.index = 0,
};
static struct dwc3_device usb_otg_ss2 = {
.maximum_speed = USB_SPEED_SUPER,
.base = DRA7_USB_OTG_SS2_BASE,
.tx_fifo_resize = false,
.index = 1,
};
static struct dwc3_omap_device usb_otg_ss2_glue = {
.base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE,
.utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
.index = 1,
};
static struct ti_usb_phy_device usb_phy2_device = {
.usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER,
.index = 1,
};
int board_usb_init(int index, enum usb_init_type init)
{
enable_usb_clocks(index);
switch (index) {
case 0:
if (init == USB_INIT_DEVICE) {
usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL;
usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
} else {
usb_otg_ss1.dr_mode = USB_DR_MODE_HOST;
usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
}
ti_usb_phy_uboot_init(&usb_phy1_device);
dwc3_omap_uboot_init(&usb_otg_ss1_glue);
dwc3_uboot_init(&usb_otg_ss1);
break;
case 1:
if (init == USB_INIT_DEVICE) {
usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL;
usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
} else {
usb_otg_ss2.dr_mode = USB_DR_MODE_HOST;
usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
}
ti_usb_phy_uboot_init(&usb_phy2_device);
dwc3_omap_uboot_init(&usb_otg_ss2_glue);
dwc3_uboot_init(&usb_otg_ss2);
break;
default:
printf("Invalid Controller Index\n");
}
return 0;
}
int board_usb_cleanup(int index, enum usb_init_type init)
{
switch (index) {
case 0:
case 1:
ti_usb_phy_uboot_exit(index);
dwc3_uboot_exit(index);
dwc3_omap_uboot_exit(index);
break;
default:
printf("Invalid Controller Index\n");
}
disable_usb_clocks(index);
return 0;
}
int usb_gadget_handle_interrupts(int index)
{
u32 status;
status = dwc3_omap_uboot_interrupt_status(index);
if (status)
dwc3_uboot_handle_interrupt(index);
return 0;
}
#endif
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
if (serial_tstc() && serial_getc() == 'c')
return 1;
if ((get_sysboot_value() & SYSBOOT_TYPE_MASK) == SYSBOOT_TYPE_PROD)
return 0;
#ifdef CONFIG_SPL_ENV_SUPPORT
env_init();
env_relocate_spec();
if (getenv_yesno("boot_os") == 1)
return 0;
#endif
return 1;
}
#endif
#ifdef CONFIG_DRIVER_TI_CPSW
extern u32 *const omap_si_rev;
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_addr = 2,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_addr = 3,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 2,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
int board_eth_init(bd_t *bis)
{
int ret;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
uint32_t ctrl_val;
/* try reading mac address from efuse */
mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = mac_hi & 0xFF;
mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
mac_addr[4] = (mac_lo & 0xFF00) >> 8;
mac_addr[5] = mac_lo & 0xFF;
if (!getenv("ethaddr")) {
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
if (is_valid_ethaddr(mac_addr))
eth_setenv_enetaddr("ethaddr", mac_addr);
}
mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = mac_hi & 0xFF;
mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
mac_addr[4] = (mac_lo & 0xFF00) >> 8;
mac_addr[5] = mac_lo & 0xFF;
if (!getenv("eth1addr")) {
if (is_valid_ethaddr(mac_addr))
eth_setenv_enetaddr("eth1addr", mac_addr);
}
ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
ctrl_val |= 0x22;
writel(ctrl_val, (*ctrl)->control_core_control_io1);
if (*omap_si_rev == DRA722_ES1_0)
cpsw_data.active_slave = 1;
if (board_is_dra72x_revc_or_later()) {
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID;
}
ret = cpsw_register(&cpsw_data);
if (ret < 0)
printf("Error %d registering CPSW switch\n", ret);
return ret;
}
#endif
#ifdef CONFIG_BOARD_EARLY_INIT_F
/* VTT regulator enable */
static inline void vtt_regulator_enable(void)
{
if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
return;
/* Do not enable VTT for DRA722 */
if (is_dra72x())
return;
/*
* EVM Rev G and later use gpio7_11 for DDR3 termination.
* This is safe enough to do on older revs.
*/
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
int board_early_init_f(void)
{
vtt_regulator_enable();
return 0;
}
#endif
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
if (is_dra72x()) {
if (board_is_dra71x_evm()) {
if (!strcmp(name, "dra71-evm"))
return 0;
}else if(board_is_dra72x_revc_or_later()) {
if (!strcmp(name, "dra72-evm-revc"))
return 0;
} else if (!strcmp(name, "dra72-evm")) {
return 0;
}
} else if (!is_dra72x() && (!strcmp(name, "dra7-evm") || !strcmp(name, "MAN2020_ADAPTER"))) {
return 0;
}
return -1;
}
#endif
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
//char *path;
//int ret, offs;
ft_cpu_setup(blob, bd);
/* Perform fixup only on DRA74x EVM */
#if 0
//if (board_is_dra74x_evm()) {
//if (!nand_sw_detect()) {
path = "/ocp/gpmc";
offs = fdt_path_offset(blob, path);
if (offs < 0)
goto fdt_error;
ret = fdt_shrink_to_minimum(blob);
if (ret < 0)
goto fdt_error;
ret = fdt_setprop_string(blob, offs, "status", "okay");
if (ret < 0)
goto fdt_error;
printf("SW5[0] on EVM has selected NAND mode. DTB updated to enable NAND in the OS\n");
//}
//}
return 0;
fdt_error:
printf("SW5[0] on EVM has selected NAND mode but couldn't update DTB to enable NAND in the OS\n");
#endif
return 0;
}
#endif
#ifdef CONFIG_TI_SECURE_DEVICE
void board_fit_image_post_process(void **p_image, size_t *p_size)
{
secure_boot_verify_image(p_image, p_size);
}
void board_tee_image_process(void *tee_image, size_t tee_size)
{
secure_tee_install((u32)tee_image);
}
#endif
3. Force the return value of init_omap_revision()(this function is at u-boot/arch/arm/cpu/armv7/omap5/hwinit.c) to be "DRA722_ES2_0", this is because the original return value is 0x2b9bc02f, which is exactly the ID_CODE of DRA71x SR2.1. But this ID_CODE doesn't show up at u-boot/arch/arm/include/asm/arch-omap5/omap.h, which mean all switch case for omap_revision() will go the default case, so i force the ID to be "DRA722_ES2_0".
4. I already enable debug message(i define DEBUG at u-boot/include/common.h)
5. I also add preloader_console_init() at u-boot/arch/arm/cpu/armv7/omap-common/hwinit-common.c to let u-boot can output log earlier
6. Since i already add preloader_console_init() at hwinit-common.c, so i mark the preloader_console_init() inside spl_board_init() function at boot-common.c to prevent doing that function twice.
Currently, i trace the code is stuck at vmmc_pbias_config() function ( at u-boot/arch/arm/cpu/armv7/omap5/hwinit.c). When system try to read register value (readl((*ctrl)->control_pbias)), then stuck. Here is hwinit.c file =>
/*
*
* Functions for omap5 based boards.
*
* (C) Copyright 2011
* Texas Instruments, <www.ti.com>
*
* Author :
* Aneesh V <aneesh@ti.com>
* Steve Sakoman <steve@sakoman.com>
* Sricharan <r.sricharan@ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <palmas.h>
#include <asm/armv7.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <linux/sizes.h>
#include <asm/utils.h>
#include <asm/arch/gpio.h>
#include <asm/emif.h>
#include <asm/omap_common.h>
DECLARE_GLOBAL_DATA_PTR;
u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
#ifndef CONFIG_DM_GPIO
static struct gpio_bank gpio_bank_54xx[8] = {
{ (void *)OMAP54XX_GPIO1_BASE },
{ (void *)OMAP54XX_GPIO2_BASE },
{ (void *)OMAP54XX_GPIO3_BASE },
{ (void *)OMAP54XX_GPIO4_BASE },
{ (void *)OMAP54XX_GPIO5_BASE },
{ (void *)OMAP54XX_GPIO6_BASE },
{ (void *)OMAP54XX_GPIO7_BASE },
{ (void *)OMAP54XX_GPIO8_BASE },
};
const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
#endif
void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size)
{
int i;
struct pad_conf_entry *pad = (struct pad_conf_entry *)array;
for (i = 0; i < size; i++, pad++)
writel(pad->val, base + pad->offset);
}
#ifdef CONFIG_SPL_BUILD
/* LPDDR2 specific IO settings */
static void io_settings_lpddr2(void)
{
const struct ctrl_ioregs *ioregs;
get_ioregs(&ioregs);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
}
/* DDR3 specific IO settings */
static void io_settings_ddr3(void)
{
u32 io_settings = 0;
const struct ctrl_ioregs *ioregs;
get_ioregs(&ioregs);
writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
if (!is_dra7xx()) {
writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
}
/* omap5432 does not use lpddr2 */
writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
writel(ioregs->ctrl_emif_sdram_config_ext,
(*ctrl)->control_emif1_sdram_config_ext);
if (!is_dra72x())
writel(ioregs->ctrl_emif_sdram_config_ext,
(*ctrl)->control_emif2_sdram_config_ext);
if (is_omap54xx()) {
/* Disable DLL select */
io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
& 0xFFEFFFFF);
writel(io_settings,
(*ctrl)->control_port_emif1_sdram_config);
io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
& 0xFFEFFFFF);
writel(io_settings,
(*ctrl)->control_port_emif2_sdram_config);
} else {
writel(ioregs->ctrl_ddr_ctrl_ext_0,
(*ctrl)->control_ddr_control_ext_0);
}
}
/*
* Some tuning of IOs for optimal power and performance
*/
void do_io_settings(void)
{
u32 io_settings = 0, mask = 0;
struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
/* Impedance settings EMMC, C2C 1,2, hsi2 */
mask = (ds_mask << 2) | (ds_mask << 8) |
(ds_mask << 16) | (ds_mask << 18);
io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
(~mask);
io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
(ds_45_ohm << 18) | (ds_60_ohm << 2);
writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
/* Impedance settings Mcspi2 */
mask = (ds_mask << 30);
io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
(~mask);
io_settings |= (ds_60_ohm << 30);
writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
/* Impedance settings C2C 3,4 */
mask = (ds_mask << 14) | (ds_mask << 16);
io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
(~mask);
io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
/* Slew rate settings EMMC, C2C 1,2 */
mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
(~mask);
io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
/* Slew rate settings hsi2, Mcspi2 */
mask = (sc_mask << 24) | (sc_mask << 28);
io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
(~mask);
io_settings |= (sc_fast << 28) | (sc_fast << 24);
writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
/* Slew rate settings C2C 3,4 */
mask = (sc_mask << 16) | (sc_mask << 18);
io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
(~mask);
io_settings |= (sc_na << 16) | (sc_na << 18);
writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
/* impedance and slew rate settings for usb */
mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
(usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
(~mask);
io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
(ds_60_ohm << 23) | (sc_fast << 20) |
(sc_fast << 17) | (sc_fast << 14);
writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2)
io_settings_lpddr2();
else
io_settings_ddr3();
}
static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
{0x45, 0x1}, /* 12 MHz */
{-1, -1}, /* 13 MHz */
{0x63, 0x2}, /* 16.8 MHz */
{0x57, 0x2}, /* 19.2 MHz */
{0x20, 0x1}, /* 26 MHz */
{-1, -1}, /* 27 MHz */
{0x41, 0x3} /* 38.4 MHz */
};
void srcomp_enable(void)
{
u32 srcomp_value, mul_factor, div_factor, clk_val, i;
u32 sysclk_ind = get_sys_clk_index();
u32 omap_rev = omap_revision();
if (!is_omap54xx())
return;
mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
div_factor = srcomp_parameters[sysclk_ind].divide_factor;
for (i = 0; i < 4; i++) {
srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
srcomp_value &=
~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
(div_factor << DIVIDE_FACTOR_XS_SHIFT);
writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
}
if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
for (i = 0; i < 4; i++) {
srcomp_value =
readl((*ctrl)->control_srcomp_north_side + i*4);
srcomp_value &= ~PWRDWN_XS_MASK;
writel(srcomp_value,
(*ctrl)->control_srcomp_north_side + i*4);
while (((readl((*ctrl)->control_srcomp_north_side + i*4)
& SRCODE_READ_XS_MASK) >>
SRCODE_READ_XS_SHIFT) == 0)
;
srcomp_value =
readl((*ctrl)->control_srcomp_north_side + i*4);
srcomp_value &= ~OVERRIDE_XS_MASK;
writel(srcomp_value,
(*ctrl)->control_srcomp_north_side + i*4);
}
} else {
srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
DIVIDE_FACTOR_XS_MASK);
srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
(div_factor << DIVIDE_FACTOR_XS_SHIFT);
writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
for (i = 0; i < 4; i++) {
srcomp_value =
readl((*ctrl)->control_srcomp_north_side + i*4);
srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
writel(srcomp_value,
(*ctrl)->control_srcomp_north_side + i*4);
srcomp_value =
readl((*ctrl)->control_srcomp_north_side + i*4);
srcomp_value &= ~OVERRIDE_XS_MASK;
writel(srcomp_value,
(*ctrl)->control_srcomp_north_side + i*4);
}
srcomp_value =
readl((*ctrl)->control_srcomp_east_side_wkup);
srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
srcomp_value =
readl((*ctrl)->control_srcomp_east_side_wkup);
srcomp_value &= ~OVERRIDE_XS_MASK;
writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
for (i = 0; i < 4; i++) {
while (((readl((*ctrl)->control_srcomp_north_side + i*4)
& SRCODE_READ_XS_MASK) >>
SRCODE_READ_XS_SHIFT) == 0)
;
srcomp_value =
readl((*ctrl)->control_srcomp_north_side + i*4);
srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
writel(srcomp_value,
(*ctrl)->control_srcomp_north_side + i*4);
}
while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
;
srcomp_value =
readl((*ctrl)->control_srcomp_east_side_wkup);
srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
}
}
#endif
void config_data_eye_leveling_samples(u32 emif_base)
{
const struct ctrl_ioregs *ioregs;
get_ioregs(&ioregs);
/*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
if (emif_base == EMIF1_BASE)
writel(ioregs->ctrl_emif_sdram_config_ext_final,
(*ctrl)->control_emif1_sdram_config_ext);
else if (emif_base == EMIF2_BASE)
writel(ioregs->ctrl_emif_sdram_config_ext_final,
(*ctrl)->control_emif2_sdram_config_ext);
}
void init_cpu_configuration(void)
{
u32 l2actlr;
asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr));
/*
* L2ACTLR: Ensure to enable the following:
* 3: Disable clean/evict push to external
* 4: Disable WriteUnique and WriteLineUnique transactions from master
* 8: Disable DVM/CMO message broadcast
*/
l2actlr |= 0x118;
omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr);
}
void init_omap_revision(void)
{
/*
* For some of the ES2/ES1 boards ID_CODE is not reliable:
* Also, ES1 and ES2 have different ARM revisions
* So use ARM revision for identification
*/
unsigned int rev = cortex_rev();
switch (readl(CONTROL_ID_CODE)) {
case OMAP5430_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = OMAP5430_ES1_0;
if (rev == MIDR_CORTEX_A15_R2P2)
*omap_si_rev = OMAP5430_ES2_0;
break;
case OMAP5432_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = OMAP5432_ES1_0;
if (rev == MIDR_CORTEX_A15_R2P2)
*omap_si_rev = OMAP5432_ES2_0;
break;
case OMAP5430_CONTROL_ID_CODE_ES2_0:
*omap_si_rev = OMAP5430_ES2_0;
break;
case OMAP5432_CONTROL_ID_CODE_ES2_0:
*omap_si_rev = OMAP5432_ES2_0;
break;
case DRA752_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = DRA752_ES1_0;
break;
case DRA752_CONTROL_ID_CODE_ES1_1:
*omap_si_rev = DRA752_ES1_1;
break;
case DRA752_CONTROL_ID_CODE_ES2_0:
*omap_si_rev = DRA752_ES2_0;
break;
case DRA722_CONTROL_ID_CODE_ES1_0:
*omap_si_rev = DRA722_ES1_0;
break;
case DRA722_CONTROL_ID_CODE_ES2_0:
*omap_si_rev = DRA722_ES2_0;
break;
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
}
/* for man2020 512 variant, force setting */
*omap_si_rev = DRA722_ES2_0;
//*omap_si_rev = readl(CONTROL_ID_CODE); //for read original ID
init_cpu_configuration();
}
void omap_die_id(unsigned int *die_id)
{
die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
}
void reset_cpu(ulong ignored)
{
u32 omap_rev = omap_revision();
/*
* WARM reset is not functional in case of OMAP5430 ES1.0 soc.
* So use cold reset in case instead.
*/
if (omap_rev == OMAP5430_ES1_0)
writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
else
writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
}
u32 warm_reset(void)
{
return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;
}
void setup_warmreset_time(void)
{
u32 rst_time, rst_val;
#ifndef CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC
rst_time = CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC;
#else
rst_time = CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC;
#endif
rst_time = usec_to_32k(rst_time) << RSTTIME1_SHIFT;
if (rst_time > RSTTIME1_MASK)
rst_time = RSTTIME1_MASK;
rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK;
rst_val |= rst_time;
writel(rst_val, (*prcm)->prm_rsttime);
}
void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
u32 cpu_rev_comb, u32 cpu_variant,
u32 cpu_rev)
{
omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
}
void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
u32 cpu_variant, u32 cpu_rev)
{
#ifdef CONFIG_ARM_ERRATA_801819
/*
* DRA72x processors are uniprocessors and DONOT have
* ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
* Extensions) Hence the erratum workaround is not applicable for
* DRA72x processors.
*/
if (is_dra72x())
acr &= ~((0x3 << 23) | (0x3 << 25));
#endif
omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
}
#if defined(CONFIG_PALMAS_POWER)
void vmmc_pbias_config(uint voltage)
{
u32 value = 0;
struct vcores_data const *vcores = *omap_vcores;
debug("\n***vmmc_pbias_config() start***\n");
value = readl((*ctrl)->control_pbias);
debug("\n***vmmc_pbias_config() value is: 0x%x***\n", value);
value &= ~SDCARD_PWRDNZ;
debug("\n***vmmc_pbias_config() step-1***\n");
writel(value, (*ctrl)->control_pbias);
udelay(10); /* wait 10 us */
debug("\n***vmmc_pbias_config() step-2***\n");
value &= ~SDCARD_BIAS_PWRDNZ;
writel(value, (*ctrl)->control_pbias);
debug("\n***vmmc_pbias_config() step-3***\n");
if (vcores->core.pmic->i2c_slave_addr == 0x60) {
if (voltage == LDO_VOLT_3V0)
voltage = 0x19;
else if (voltage == LDO_VOLT_1V8)
voltage = 0xa;
lp873x_mmc1_poweron_ldo(voltage);
} else {
palmas_mmc1_poweron_ldo(voltage);
}
debug("\n***vmmc_pbias_config() step-4***\n");
value = readl((*ctrl)->control_pbias);
value |= SDCARD_BIAS_PWRDNZ;
writel(value, (*ctrl)->control_pbias);
udelay(150); /* wait 150 us */
value |= SDCARD_PWRDNZ;
writel(value, (*ctrl)->control_pbias);
udelay(150); /* wait 150 us */
debug("\n***vmmc_pbias_config() done***\n");
}
#endif
Regards,
Shawn
Hi RK,
Update the latest status,
I found the reason of stuck at vmmc_pbias_config() is because our memory register setting(lisa_map at evm.c), the system can go further after correct it.
But now, system still stuck at u-boot, here is the log => boot_log (4).txt
It seems that system can't recognize MMC-1 device(SD card). Do you have any advice for debug?
Regards,
Shawn
Hi Shawn,
You can refer to below dts file for example on dra71 + tps6591x combination. This is from a different Kernel version, but is a good reference.
http://git.ti.com/ti-linux-kernel/ti-linux-kernel/blobs/ti-lsk-linux-4.14.y/arch/arm/boot/dts/dra71-lcard.dts
Regards,
Vishal