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TDA2EXEVM: Register vales to drive Timer in PWM mode

Priyanka Zadge
Prodigy 170 points

Part Number: TDA2EXEVM

Hi,

I want to achieve PWM output of 100HZ frequency with 60% duty cycle(High polarity)

For this to achieve , I have set TCLR register in 

1. Auto-reload mode

2.Compare bit is enabled

3.Overflow and match trigger is enabled

4.Pulse modulation is chosen

5.Prescalar chosen is 1.

I have set TLDR value equal to TON period of duty cycle i.e. for 6ms

Now, i want to understand, how TMAR and TLDR registers should be chosen in order to achieve 100Hz pwm with 60% duty cycle.

Basically,

if TCRR register gets reloaded to TLDR value after overflow then how does it behave to on match with TMAR register value.

Regards,

Priyanka Zadge

  • 0
    Prodigy 170 points

    Hello,

    Gentle Remainder..

    Regards,

    Priyanka Zadge

  • 0 in reply to Priyanka Zadge
    TI__Genius 17720 points
    Hi Priyanka,

    You didn't mention the clock frequency fed to timer.

    Stan
  • 0
    TI__Mastermind 27743 points

    Priyanka,

    As Stan mentioned please specify timer number you want to use and input frequency for that.

  • 0 in reply to Stanislav Stilyanov
    TI__Genius 17720 points

    Priyanka,

    I did a quick search in the TDA2x TRM. Most of the information is present section 22.2.4.10 Pulse-Width Modulation. And the required bits to set are listed in 22.2.5.2.4 GP Timer PWM Mode.

    Firstly, please see Figure 22-13. Timing Diagram of PWM With TCLR[7] SCPWM Bit = 0, with config Timer PWM (TRG = 0b10 and PT = 1).

    In this mode, timer overflow event (FFFF FFFF --> 0000 0000)  triggers a positive edge on PWM pin and reaching a match value (TMAR) triggers a falling edge.

    That is, frequency will depend on the period between two timer overflows, which in turn is dependent on the frequency (and a possible pre-scaler) which clocks the timer. Match value, on the other hand, will adjust the duty cycle. E.g match value of 7FFF FFFF will result in duty cycle of 50%.

    However, a 32-bit timer has a huge period to overflow that will need the same huge frequency even for only 100Hz. To keep things simple, one may use only 8-bits (may be more, but 8-bit is a good example) of the timer by auto-load the value of FFFF FF00 from TLDR. This will obviously cause the timer to overflow much sooner.

    With this regard, please see if 8-bit (or the resolution you eventually choose) resolution is enough for your application. Also note that now the matching value would be FFFF FF7F for 50% PWM in this case.

    For an 8-bit timer, you will need only 256 Hz timer clock for a one-second overflow and respectively 25 600 Hz for 100 Hz PWM frequency.

    I don't know the TI timers in detail but the theory must be close to the above and hope that will be of some help.

    Regards,

    Stan

  • 0 in reply to Stanislav Stilyanov
    Prodigy 170 points

    Hi Stan,

    Thank for your support.

    Regards,

    Priyanka Zadge