RTOS/AM5716: EDMA buffer cached issue

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I just see a post for another processor. I believe I had the same issue. I am wondering what is the solution if my buffers have to be in external memory?  

Your help is appciated!

In reply to Manjula Ellepola:

Hi Sivaraj

Ok solved the problem. I allocated the buffers in L2 Ram (after reading another ton of docs on how to do this :))and everything works as expected. So it was indeed the cache coherence problem. I wonder how many other newbies get caught out with this. If you remember my earlier posts I had problems writing out the transmit stream via edma to McAsp. I never got a proper answer for this from TI. Now I know for sure that this was also caused by the coherence problem. It was funny at the time that I had to align the buffers to 128byte boundary and the problem got solved but really didn't know the reason why.
(Newbies pls look at the c674x cache manual...it has got very good info on this issue when buffers reside in external memory and you use dma to xfer data).

I am pressing on with this processor fingers crossed.... :)

Thanks and regards

Manjula

Hi,

Your buffer is inside DDR. Can you check if your DDR is cached and L2 is cached as well? For example, in your code, do you have something like :

CACHE_enableCaching(128);
...
CACHE_enableCaching(159);
CACHE_setL2Size(CACHE_256KCACHE);

Or something in the .cfg like:
Cache.setMarMeta(0x80000000, 0x20000000, Cache.PC | Cache.PCX | Cache.PFX | Cache.WTE);

If you are not sure, you can look at the registers with CCS/JTAG. See the AM572x TRM, Table 5-13. DSP_ICFG Registers Mapping Summary. MARk registers for DDR and L2CFG for L2.

I think you have DDR and L2 cached. Please confirm. Then in the CCS memory view, there is check for L1Dcache and L2 cache. If they are checked, it is cache view.

When you have CPU writes a new data into the buffer, can you see it in cached view or non-cached view from CCS memory window? Then you do a cache_wb, can you see the new data in the non-cached view? Also, you mentioned you can write a new data via CCS window and MCASP can transfer the new data out correctly, the new data is in the non-cached view, correct?

Regards, Eric

Hi Eric,

Thank you so much for your response.

I had checked :
1) there is no any cached enable/disable function in my code.
2) there is no Cache.setMarMeta() in .cfg file
3)when CPU writes a new data into the buffer, I can see it in cached view, not in non-cached view from CCS memory view. I can see only the old data on scope monitoring output of McASP1 , not new ones written by CPU. I also made McASP loopback, and I did not see new data in input buffers. If I manually write a new data in output buffers from cached or non-cached CCS memory view, I see the new data on scope, but I still did not see this new data in input buffer. I never see any data in non-cached view, but if I just write a new data, I see it in scope.

I was trying to check if L2 and DDR are cached. I check the register in table 5-13 (for AM5716), but I did not see a bit for enable/disable L2 or DDR cache. I only see "cachable " in CACHE_MMU_xxxx_POLICY_i, and it is not set. Could you tell me which register is for setting mark bit for L2 or DDR?

thanks,

Ron

Hi Eric,

I am using CCS to download my application to DSP core. I found after I connected to target(run gel script) before I load program, I see the DDR MAR bit is set to C, that is no cachable. however, after I load my program to DSP core, but not run it yet, I see the MAR bit change to D, that is, PC is set for cacheable. what could made this change?

Thanks,

Ron

Hi Eric,

I added code to disable cache for the DDR region(MAR172) by set PC bit to 0. however, I got following error. 0xac101f00 is one of my ping pong buffer's address.  If  i enable the cache, then this error is gone.  

Trouble Reading Memory Block at 0xac101f00 on Page 0 of Length 0x4:
(Error -1202 @ 0xAC101F00)
Device core is hung. The debugger will attempt to force the device to a ready state to recover debug control. Your application's state will be corrupt. You should have limited access to memory and registers, but you may need to reset the device to debug further.
(Emulation package 6.0.628.3)

Thanks,

Ron

Hi,

Can you clarify what program you are running for MCASP test? Is it a TI CCS project example or your own code? Is it run on C66x? Is it a SYSBIOS project? 

Regards, Eric