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AM4376: MMC timing specification

shigehiro tsuda
Mastermind 9490 points
Part Number: AM4376


Hi,

Our customer is considering devices connecting with AM4376 MMC1 or MMC2 interface.

It is used in the following.
· CLK frequency 48MHz
· Voltage 1.8V

The specifications of MMC of AM4376 refer to the following in the datasheet.
Table 5-127. Timing Requirements for MMC [1/2] _ CMD and MMC [1/2] _DAT [7: 0]
Table 5-130. Switching Characteristics for MMC [x] _ CMD and MMC [x] _DAT [7: 0] - HSPE = 1

AM437x Specification

· Delay time td(CLKL-DAT) :(Min) 0.8 ns
· Delay time td(CLKL-CMD) :(Min) 0.8 ns

· Hold time th(CLKH-DATV) :(Min) 2.55 ns
· Hold time th(CLKH-CMDV) :(Min) 2.55 ns

Specification of connected device

· Delay time td(CLKL-DAT) :(Min) 2.5 ns
· Delay time td(CLKL-CMD) :(Min) 2.5 ns

· Hold time th(CLKH-DATV) :(Min) 2.0 ns
· Hold time th(CLKH-CMDV) :(Min) 2.0 ns

Are the above specifications acceptable as specifications of the AM4376 device?
If it is not acceptable, can only be adjusted with external resistance or capcitor?
Please tell me if there is other workaround.

I also see the data sheet of other devices of the TI processor(AM335x,AM57xx etc),
This timing specification is different.

I understand that MMC of AM4376 is created by JEDEC standard.
Is it correct with the recognition that it can be used without problems if it is a device of the JEDEC standard?

Best Regards,
Shigehiro Tsuda

  • 0
    TI__Guru**** 393215 points
    The factory team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru 63525 points

    Your first question cannot be answered without including actual PCB delays in any peripheral timing analysis.

    There may be cases where a resistor/capacitor network can be used to delay a signal and help with timing, but this approach can be problematic. Inserting additional signal trace on the PCB to adjust timing may be a better approach. 

    Timing requirements are given to the SOC design team and they make internal adjustments with the goal of meeting the requirements. The values provided are based on the respective peripheral industry standard, when applicable, and includes some assumptions about expected PCB trace delays. Once silicon is available, the product engineering team characterizes timing of the various peripherals. The data sheet values represent characterization data. 

    In many cases there are trade-offs in a design that need to be considered and what must be done to benefit one function may compromising another. When this happens it may not be possible to meet all of our timing goals. So we publish the characterized values in the data sheet and leave some timing adjustments to the systems/PCB designer. 

    This is why timing values may vary from one device to another. This is also the reason timing analysis should be performed on every peripheral using actual PCB delays. 

    For the case mentioned in your E2E post, the effect of attached device min delay on the processor hold time should not be a problem since the processor to device clock delay and device to processor CMD/DAT delay will provide additional margin. However, the effect of processor min delay on the attached device hold time will be a problem if the system designer doesn’t insert at least 1.2ns additional delay on the CMD/DAT traces. 

    Regards,
    Paul

  • 0 in reply to peaves
    TI__Guru 63525 points
    I just realized the comment about needing to insert 1.2ns of delay may not be correct. My initial assumption was based on the attached device having a hold requirement on the same clock edge as CMD/DAT changes. If the attached device has a hold time requirement relative to the rising edge of clock and the CMD/DAT signals from the processor are changing on the falling edge of clock (HSPE=0), the hold time will be half of the clock period +/- the signal trace delay differences.

    Regards,
    Paul
  • 0 in reply to peaves
    Mastermind 9490 points

    Hi Paul,

    Thank you for quick reply.
    Our customers use at high speed (48 MHz).
    Although the timing is delayed,is there the problem as SD controller by using HSPE=0?

    Best Regards,
    Shigehiro Tsuda

  • 0 in reply to shigehiro tsuda
    TI__Guru 63525 points

    The HSPE bit only selects the clock edge used to change output data.  So this bit can be configured to either value as necessary to optimize timing of the attached device.

    Regards,
    Paul

  • 0 in reply to peaves
    Mastermind 9490 points

    Hi Paul,

    Thank you for quick reply.

    When HSPE = 0, td(CLKL-CMD) and td(CLKL-CMD) are MAX 14ns when checking the following in the datasheet.
    Table 5-129. Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—HSPE=0

    When MMC_CLK is used at 48MHz, the half cycle becomes 10.4ns, so there is a possibility that DATA has not changed at the rising edge of CLK.
    When MMC_CLK is used at 48MHz, is it really a problem with HSPE=0?
    If there is no problem, it seems that the MAX value of td(CLKL-CMD) and td(CLKL-CMD)in the datasheet is incorrect.

    Best Regards,
    Shigehiro Tsuda

  • 0 in reply to shigehiro tsuda
    TI__Guru 63525 points

    I understand the question.

    Using HSPE=0 creates a very large setup time violation based on the max delay values published in the data manual.  This requires the frequency of operation to be reduced to resolve the setup violation.

    Using HSPE=1 creates a 1.2ns hold time violation, which requires the PCB designer to insert additional delay in the CMD and DAT signal traces.

    I will need a few days to determine if the max delay values published in the data manual for HSPE=0 is correct.

    Regards,
    Paul

  • 0 in reply to peaves
    Mastermind 9490 points

    Hi Paul,

    Thank you for quick reply.
    It will take a few days to decide it, I understand.
    We will wait for your answer.

    Best Regards,
    Shigehiro Tsuda

  • 0 in reply to shigehiro tsuda
    TI__Guru 63525 points

    We determined the delay values in Table 5-129 of the AM437x data manual are not correct. When the AM437x data manual was created, this table was copied from the AM335x data manual and the values were never updated.

     

    I will submit an internal request to update the AM437x data manual with the correct values.

     

    The minimum delay value for parameter #10 and #11 in Table 5-129 for both operating voltages should be -7.4ns.

    The maximum delay value for parameter #10 and #11 in Table 5-129 for both operating voltages should be 4.4ns.

     

    These values should provide setup and hold margin at 48MHz with HSPE=0.

     

    Regards,

    Paul

  • 0 in reply to peaves
    Mastermind 9490 points

    Hi Paul,

    Thank you for your quick support.
    I understand that these values ​​in the AM437x data sheet were not correct.

    I will answer the correct value to the customer.
    Thank you for updating the datasheet.

    Best Regards,
    Shigehiro Tsuda