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DDR2 trace lenght

Joaquin Gonzalez
Expert 1200 points

Hi to everyone,

I would like to ask some questions about SPRAAL6A "implementing ddr2 pcb layout...". 

On table 11 parameter 1 it says that center to center DQS to other DDR2 trace spacing must be minimum 4w, but (attending to note 2) it also says that this spacing is allowed to fall to minimum (w) for up to 500 mil.

- Does this means that this spacing can be w for 500 mil?  If my traces are w=4mil, that would mean a shorcircuit if I measure the spacing from center to center.

-Also, Does parameter 6 on Table 11 mean spacing between DQ traces within the same byte?

Thanks

 

  • 0
    TI__Mastermind 41665 points

    Nuba said:
    - Does this means that this spacing can be w for 500 mil?  If my traces are w=4mil, that would mean a shorcircuit if I measure the spacing from center to center.

    My understanding is that the note is just implying that you can go under the 4w minimum specification for up to 500 mils of the trace, the minimum of w is just the physical minimum, as you point out since each trace is w wide this implies geometrically that you have a short if the center to center width is not greater than w.

    Nuba said:
    -Also, Does parameter 6 on Table 11 mean spacing between DQ traces within the same byte?

    Yes, for spacing between DQ traces of different bytes you would use 4w as a trace from another byte is considered 'other DDR2 trace' as mentioned in note 6 under table 11.

  • 0 in reply to Bernie Thompson TI
    Expert 1200 points

    Thanks for the answer.

    Moreover I have 2 more questions:

     At the same table, it is said that a 16 bit ddr will have 2 sets of data net classes (0 and 1) (note 3).

    -Does note 5 and 7 mean that DQ0 and DQS0 can have a different manhattan distance than DQ1 and DQS1, and that you don't need to skew match both groups?

    My second question is regarding impedance matching:

    - If  Zo needs to be constant within  trace length, am I right if I change the trace width when I go from a microstrip (w=6) to a stripline (w=4) in order to keep z=50?

    Thanks a lot in advance.

     

     

     

  • 0 in reply to Joaquin Gonzalez
    TI__Mastermind 41665 points

    Nuba said:
    -Does note 5 and 7 mean that DQ0 and DQS0 can have a different manhattan distance than DQ1 and DQS1, and that you don't need to skew match both groups?

    Yes, each individual byte is not dependent on the other byte(s) for skew matching.

    Nuba said:
    - If  Zo needs to be constant within  trace length, am I right if I change the trace width when I go from a microstrip (w=6) to a stripline (w=4) in order to keep z=50?

    This sounds correct however this is getting to the edge of my expertise in layouts, so I will have to verify this one.

  • 0 in reply to Bernie Thompson TI
    TI__Mastermind 41665 points

    Bernie Thompson said:
    This sounds correct however this is getting to the edge of my expertise in layouts, so I will have to verify this one.

    I looked into this and this is definately a way to do handle impedance matching, one suggestion though would be to have the board house handle the impedance matching though, I understand that they will usually take care of this sort of thing for you if you tell them what traces you want impedance matched.