TMS320C6746: Problem with PLL0init

Hi,

I've notified the design team. They will post their feedback directly here.

Best Regards,
Yordan

Hi Kirill
Can you share the PLL0Init code that you are talking about here and point to the exact lines of code that the code is stuck?
Why is there a need to do a second initialization of PLL0?

Additional follow up questions
1) You seem to highlight that you are following the datasheet recommendations for filtering and also using an external osc for ESD noise immunity (as recommended in the device errata) - but why do you think these have something to do with your failure. Are the 50 boards exposed to some noise/ESD strikes environment?
2) Do you have more details on 2 out 50 test passing/failing. Are these field failures or issues found during production shipment? Are all boards tested to same condition (sw) and similar sequence does not fail on 48 boards?
3) Do you have the ability to observe the OBSCLK on your board
here are some e2e post for obsclk enabling
e2e.ti.com/.../1818495



You mention votlage levels etc, but I do not know if that is just voltage drop with high activity vs low activity . If in the failing condition the DSP is just spinning in a loop polling for PLL stat, you may see similar voltage levels on a working board too, just mimicking the same code loop. I do not understand the significance of those observations.

Hi Kirill
I have not heard from you for a while , were you able to resolve the issue?
Regards
Mukul

Hi, Mukul

Here is code for PLL0init:

#define OSCIN_HZ	25000000ul	// frequency of quartz on the board = 25 mhz
#define PLL0CLKMODE	1		// 1 = External Oscilator (Square wave)
#define CPU_FREQ_HZ	450000000ul	// required operating frequency = 450 mhz

#define PLL0PREDIV	1	// F / 1..32
#define PLL0MULT	(CPU_FREQ_HZ/OSCIN_HZ) // F * 1..32
#define PLL0POSTDIV	1	// F / 1..32
#define PLL0DIV1	1	// F / 1..32
#define PLL0DIV2	2	// F / 1..32
#define PLL0DIV3	3	// F / 1..32
#define PLL0DIV4	4	// F / 1..32
#define PLL0DIV5	3	// F / 1..32
#define PLL0DIV6	1	// F / 1..32
#define PLL0DIV7	6	// F / 1..32

//-----------------------------------------------------------------------------
//	7. Phase-Locked Loop Controller (PLLC)
//
//	PLLC0 from 01C11000h
//
// 01C11000h REVID PLLC0 Revision Identification Register
// 01C110E4h RSTYPE PLLC0 Reset Type Status Register
// 01C110E8h RSCTRL PLLC0 Reset Control Register
// 01C11100h PLLCTL PLLC0 Control Register
// 01C11104h OCSEL PLLC0 OBSCLK Select Register
// 01C11110h PLLM PLLC0 PLL Multiplier Control Register
// 01C11114h PREDIV PLLC0 Pre-Divider Control Register
// 01C11118h PLLDIV1 PLLC0 Divider 1 Register
// 01C1111Ch PLLDIV2 PLLC0 Divider 2 Register
// 01C11120h PLLDIV3 PLLC0 Divider 3 Register
// 01C11124h OSCDIV PLLC0 Oscillator Divider 1 Register
// 01C11128h POSTDIV PLLC0 PLL Post-Divider Control Register
// 01C11138h PLLCMD PLLC0 PLL Controller Command Register
// 01C1113Ch PLLSTAT PLLC0 PLL Controller Status Register
// 01C11140h ALNCTL PLLC0 Clock Align Control Register
// 01C11144h DCHANGE PLLC0 PLLDIV Ratio Change Status Register
// 01C11148h CKEN PLLC0 Clock Enable Control Register
// 01C1114Ch CKSTAT PLLC0 Clock Status Register
// 01C11150h SYSTAT PLLC0 SYSCLK Status Register
// 01C11160h PLLDIV4 PLLC0 Divider 4 Register
// 01C11164h PLLDIV5 PLLC0 Divider 5 Register
// 01C11168h PLLDIV6 PLLC0 Divider 6 Register
// 01C1116Ch PLLDIV7 PLLC0 Divider 7 Register
// 01C111F0h EMUCNT0 PLLC0 Emulation Performance Counter 0 Register
// 01C111F4h EMUCNT1 PLLC0 Emulation Performance Counter 1 Register

#define PLLC0_BASE_ADDR		0x01C11000ul

#define PLLC0_REVID		(*(volatile unsigned*)(PLLC0_BASE_ADDR+  0x0))
#define PLLC0_RSTYPE		(*(volatile unsigned*)(PLLC0_BASE_ADDR+ 0xE4))
#define PLLC0_RSCTRL		(*(volatile unsigned*)(PLLC0_BASE_ADDR+ 0xE8))
#define PLLC0_PLLCTL		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x100))
#define PLLC0_OCSEL		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x104))
#define PLLC0_PLLM		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x110))
#define PLLC0_PREDIV		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x114))
#define PLLC0_PLLDIV1		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x118))
#define PLLC0_PLLDIV2		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x11C))
#define PLLC0_PLLDIV3		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x120))
#define PLLC0_OSCDIV		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x124))
#define PLLC0_POSTDIV		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x128))
#define PLLC0_PLLCMD		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x138))
#define PLLC0_PLLSTAT		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x13C))
#define PLLC0_ALNCTL		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x140))
#define PLLC0_DCHANGE		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x144))
#define PLLC0_CKEN		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x148))
#define PLLC0_CKSTAT		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x14C))
#define PLLC0_SYSTAT		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x150))
#define PLLC0_PLLDIV4		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x160))
#define PLLC0_PLLDIV5		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x164))
#define PLLC0_PLLDIV6		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x168))
#define PLLC0_PLLDIV7		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x16C))
#define PLLC0_EMUCNT0		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x1F0))
#define PLLC0_EMUCNT1		(*(volatile unsigned*)(PLLC0_BASE_ADDR+0x1F4))

//-----------------------------------------------------------------------------
//	10. System Configuration (SYSCFG) Module
//
//	SYSCFG0 from 01C14000h
//
// 01C14000h REVID Revision Identification Register
// 01C14008h DIEIDR0 Die Identification Register 0
// 01C1400Ch DIEIDR1 Die Identification Register 1
// 01C14010h DIEIDR2 Die Identification Register 2
// 01C14014h DIEIDR3 Die Identification Register 3
// 01C14018h DEVIDR0 Device Identification Register 0
// 01C14020h BOOTCFG Boot Configuration Register
// 01C14038h KICK0R Kick 0 Register
// 01C1403Ch KICK1R Kick 1 Register
// 01C14044h HOST1CFG Host 1 Configuration Register
// 01C140E0h IRAWSTAT Interrupt Raw Status/Set Register
// 01C140E4h IENSTAT Interrupt Enable Status/Clear Register
// 01C140E8h IENSET Interrupt Enable Register
// 01C140ECh IENCLR Interrupt Enable Clear Register
// 01C140F0h EOI End of Interrupt Register
// 01C140F4h FLTADDRR Fault Address Register
// 01C140F8h FLTSTAT Fault Status Register
// 01C14110h MSTPRI0 Master Priority 0 Register
// 01C14114h MSTPRI1 Master Priority 1 Register
// 01C14118h MSTPRI2 Master Priority 2 Register
// 01C14120h-01C1416Ch PINMUX0-19 Pin Multiplexing Control 0-19 Register
// 01C14170h SUSPSRC Suspend Source Register
// 01C14174h CHIPSIG Chip Signal Register
// 01C14178h CHIPSIG_CLR Chip Signal Clear Register
// 01C1417Ch-01C1418Ch CFGCHIP0-4 Chip Configuration 0-4 Register

#define SYSCFG0_BASE_ADDR	0x01C14000ul

#define SYSCFG0_REVID		(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+  0x0))
#define SYSCFG0_DIEIDR0		(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+  0x8))
#define SYSCFG0_DIEIDR1		(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+  0xC))
#define SYSCFG0_DIEIDR2		(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+ 0x10))
#define SYSCFG0_DIEIDR3		(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+ 0x14))
#define SYSCFG0_DEVIDR0		(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+ 0x18))
#define SYSCFG0_BOOTCFG		(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+ 0x20))
#define SYSCFG0_KICK0R		(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+ 0x38))
#define SYSCFG0_KICK1R		(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+ 0x3C))
#define SYSCFG0_HOST1CFG	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+ 0x44))
#define SYSCFG0_IRAWSTAT	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+ 0xE0))
#define SYSCFG0_IENSTAT		(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+ 0xE4))
#define SYSCFG0_IENSET		(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+ 0xE8))
#define SYSCFG0_IENCLR		(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+ 0xEC))
#define SYSCFG0_EOI		(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+ 0xF0))
#define SYSCFG0_FLTADDRR	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+ 0xF4))
#define SYSCFG0_FLTSTAT		(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+ 0xF8))
#define SYSCFG0_MSTPRI0		(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x110))
#define SYSCFG0_MSTPRI1		(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x114))
#define SYSCFG0_MSTPRI2		(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x118))
#define SYSCFG0_PINMUX00	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x120))
#define SYSCFG0_PINMUX01	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x124))
#define SYSCFG0_PINMUX02	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x128))
#define SYSCFG0_PINMUX03	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x12C))
#define SYSCFG0_PINMUX04	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x130))
#define SYSCFG0_PINMUX05	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x134))
#define SYSCFG0_PINMUX06	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x138))
#define SYSCFG0_PINMUX07	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x13C))
#define SYSCFG0_PINMUX08	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x140))
#define SYSCFG0_PINMUX09	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x144))
#define SYSCFG0_PINMUX10	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x148))
#define SYSCFG0_PINMUX11	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x14C))
#define SYSCFG0_PINMUX12	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x150))
#define SYSCFG0_PINMUX13	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x154))
#define SYSCFG0_PINMUX14	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x158))
#define SYSCFG0_PINMUX15	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x15C))
#define SYSCFG0_PINMUX16	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x160))
#define SYSCFG0_PINMUX17	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x164))
#define SYSCFG0_PINMUX18	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x168))
#define SYSCFG0_PINMUX19	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x16C))
#define SYSCFG0_SUSPSRC		(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x170))
#define SYSCFG0_CHIPSIG		(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x174))
#define SYSCFG0_CHIPSIG_CLR	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x178))
#define SYSCFG0_CFGCHIP0	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x17C))
#define SYSCFG0_CFGCHIP1	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x180))
#define SYSCFG0_CFGCHIP2	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x184))
#define SYSCFG0_CFGCHIP3	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x188))
#define SYSCFG0_CFGCHIP4	(*(volatile unsigned*)(SYSCFG0_BASE_ADDR+0x18C))

// 10. System Configuration (SYSCFG) Module
#define syscfgKickUnlock()	(void)(SYSCFG0_KICK0R = 0x83e70b13, SYSCFG0_KICK1R = 0x95a4f1e0)

#define PLLEN_MUX_SWITCH	4
#define PLL_LOCK_TIME_CNT	2400

// Initializing PLL Mode from PLL Power Down
void pllc0Init(void)
{
	volatile unsigned i;
	// Unlock Device
	syscfgKickUnlock();
	// Clear PLL_MASTER_LOCK
	SYSCFG0_CFGCHIP0 &= ~(1u<<4);

	// 1. Program the CLKMODE bit in PLLC0 PLLCTL
	PLLC0_PLLCTL &= ~(1u<<8);
	PLLC0_PLLCTL |= (PLL0CLKMODE << 8);
	// 2. Switch the PLL to bypass mode:
	// a. Clear the PLLENSRC(5) bit in PLLCTL to 0
	PLLC0_PLLCTL &= ~(1u<<5);
	// b. For PLL0 only, select the clock source by programming the EXTCLKSRC(9) bit in PLLCTL
	PLLC0_PLLCTL &= ~(1u<<9);
	// c. Clear the PLLEN(0) bit in PLLCTL to 0 (PLL in bypass mode)
	PLLC0_PLLCTL &= ~(1u<<0);
	// d. Wait for 4 OSCIN cycles to ensure that the PLLC has switched to bypass mode.
	for (i=0; i<PLLEN_MUX_SWITCH; i++);
	// 3. Clear the PLLRST(3) bit in PLLCTL to 0 (resets PLL)
	PLLC0_PLLCTL &= ~(1u<<3);
	// 4. Clear the PLLPWRDN(1) bit in PLLCTL to 0 (brings PLL out of power-down mode)
	PLLC0_PLLCTL &= ~(1u<<1);
	// 5. Program the desired multiplier value in PLLM. Program the POSTDIV, as needed
	PLLC0_PREDIV  = (1u<<15)|(PLL0PREDIV-1);
	PLLC0_PLLM = (PLL0MULT-1);
	PLLC0_POSTDIV = (1u<<15)|(PLL0POSTDIV-1);
	// 6. If desired, program PLLDIVn registers to change the SYSCLKn divide values:
	// a. Wait for the GOSTAT bit in PLLSTAT to clear to 0
	while ((PLLC0_PLLSTAT & (1u<<0)) != 0);
	// b. Program the RATIO field in PLLDIVx
	PLLC0_PLLDIV1 = (1u<<15)|(PLL0DIV1-1);
	PLLC0_PLLDIV2 = (1u<<15)|(PLL0DIV2-1);
	PLLC0_PLLDIV3 = (1u<<15)|(PLL0DIV3-1);
	PLLC0_PLLDIV4 = (1u<<15)|(PLL0DIV4-1);
	PLLC0_PLLDIV5 = (1u<<15)|(PLL0DIV5-1);
	PLLC0_PLLDIV6 = (1u<<15)|(PLL0DIV6-1);
	PLLC0_PLLDIV7 = (1u<<15)|(PLL0DIV7-1);
	// c. Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition
	PLLC0_PLLCMD |= (1u<<0);
	// d. Wait for the GOSTAT bit in PLLSTAT to clear to 0
	while ((PLLC0_PLLSTAT & (1u<<0)) != 0);
	// 7. Set the PLLRST bit in PLLCTL to 1 (brings PLL out of reset)
	PLLC0_PLLCTL |= (1u<<3);
	// 8. Wait for PLL to lock. See PLL spec for PLL lock time
	for (i=0; i<PLL_LOCK_TIME_CNT; i++);
	// 9. Set the PLLEN bit in PLLCTL to 1 (removes PLL from bypass mode)
	PLLC0_PLLCTL |= (1u<<0);

	// SET PLL lock bit
	SYSCFG0_CFGCHIP0 |= (1u<<4);
}

void main()
{
	/// ... some init ...

	pllc0Init(); ///< ok
	pllc0Init(); ///< reset?

	/// does not reach this place
}

Reason for 2 initializations of PLLs is that there is loader that do first initialization, than it loads test program that have another initialization. Maybe it is bad idea to use 2 initializations, but there is no such resctrictions in documentation, and we afraid that "failure" boards can have more complex problems that may occur after shipment in operation.

Answers for additional questions:

1) Our boards must have high noise immunity, thats why we use this recommendations. My first thoughts about this problem was with DC Resistance of DLP11SN900HL2L that is 1,5Ohm. It is higher than DC resistance of DLW21SN900SQ2 (0,35Ohm) that we use in previous revisions of this boards. We tried to use only two wires with low resistance instead of filters, but it has no effect, we still have this failures.

2) All failures were find while testing boards before final assembly. All boards pass the same test stand with same SW. Other boards pass this test without this problem.

3) About observing the OBSCLK we wiil try it later, now we assembling one more test stand to emulate this falures.

4) We try to use PLL0init on good boards 2 times, but it has no effect, boards still works fine.

Regards

Kirill

Hi Kirill
Thanks for sharing additional details. Nothing immediately pops out as an issue

Few more follow up questions
1) Can you share where exactly the code gets stuck or crashes? Is it somewhere in the second pll init routine or post this routine?
2) You mentioned that the failure is the inability to read/write internal memory? Which internal memory? Do you have jtag connection, and if so do you get an error message trying to connect to emulator - if so please share the error messagee
3) If you think that it is the 2nd init that is causing the issue, i am assuming you can just run the pll init code multiple time to see if you see clear difference between a working vs failing board?
4) Please confirm that RAM supplies - RVDD )pins (E5, H14, N7) are connected properly?
5) Is EMI noise filter the only BOM change between new and old boards?
6) Did the old boards get go through the same test prior to final assembly?

Regards
Mukul

Hi Mukul

1) It crash somewhere in PLL0init code, but I cant say where is. We can investigate this but we need time for it until 11 may i think.

2) Our programmer said that is L2 cache. But he mentioned that if DSP stuck after second PLL0init we still can upload to it new program by HPI bus and it will go to normal operation state.

3) As I said before we try to run PLL0init multiple times on "bad" and "good" boards. Results are same, "good" boards works fine, "bad" boards are stuck.

4) RVDD connected to 1,3V rail through TPS62590DRV.

5) Filters swaped from bottom of PCB to top, closer to DSP. There is some more minor changes, but they dont concern this problem.

6) Yes, all boards get through the same test prior to final assembly.

Also I want to ask, what reason to observe OBSCLK?