We want to build PCIe interface between C6678 and "RoHS-compliant SmartFusion®2 SoC FPGA Security Evaluation Kit (M2S090TS-EVAL-KIT)". To test the interface we used TMDSEVM6678 eval board. We've made adapter board to connect the two eval board together. We connected one lane and want to use it in GEN2 mode. DSP will be RC and FPGA will be EP. To test connection we are using TI example in pdk_c667x_2_0_7.
The test code always get stuck in link up. When I check LTSSM state it is changing between 1,2,6 periodically. we have provided external clock of 100Mhz to both eval boards reference clocks.
can you suggest any solutions?
Thank you,
Shurooq
