PCI master burst in fifo desitation

Let me clarify my question:

Is it possible to burst in PCI master in fifo address mode ?

Guy

When you say fifo address mode I assume you are meaning the configuration you are using in the EDMA3? I do not believe this will allow the PCI to burst as a bus master, though I am not very familiar with the low level PCI protocol, my understanding is that when you burst on a PCI bus by the standard that the target is assuming that the address will increment for each new piece of data coming across the bus during the burst. Therefore if you wrote to just one address repeatedly in the PCI master memory map (such as with the EDMA3 FIFO mode) you would only get individual accesses on the PCI bus to the same address. I suspect this is the issue, though hopefully someone more familiar with the inner workings of the PCI bus can comment.

Yes I'm meaning EDMA3 configuration for fifo address mode.

I will try to shunk the dma transfert to stay in the fifo space on the device and be able to have a long transfert without intervention.

Thank's

Guy