We are in the process of verifying theoretical cycle time calculations for a convolution function, based on information from the generated asm file.
Following results and questions pertain to the attached file conv.c.txt and a section of the generated conv.asm file (please see below).
conv.c implements a basic convolution function.
Our setup details are :
- EVM6472, used to run .out file generated from a SYS/BIOS based
project
- CCS v4.2
- SYS/BIOS (BIOSv6)
- CGT v7.0.3
There appears to be a mismatch in timing measurements, with "actual run time" being about 9 times the "computed run time".
From the C code,
Number of outer loop iterations = x_len + h_len = 196000+36000 = 232000
Number of inner loop iterations = h_len = 36000
From asm file, Cycle time for software pipelined loop is
Total cycles (est) = 10 + trip_cnt * 2, with 2 DOTP2 instructions for a SINGLE SCHEDULED ITERATION.
Hence, computed run time = x_len*(10+trip_cnt*2),
trip_cnt = h_len/4 (2 DOTP2's per iteration)
Therefore,
Computed run time = x_len*(10+h_len/2) = 4178320000 cycles.
At 700Mhz, this would correspond to a time of 6s (approx).
However actual run time of the program was determined to be ~52 s. Run time was calculated by inserting SYS/BIOS (BIOS6) Clock_getTicks() calls right before and immediately after the outer loop. Also, we made sure that interrupts were disabled during execution of the loops, this had no effect on run time measured.
(1) Is there something wrong with how "Computed run time" is being calculated or how we are measuring "Actual run time" ?
(2) As part of the Software Pipeline information, the compiler outputs a line that reads something like "ii = 2 Schedule found with 6 iterations in parallel". Does the word "iterations" in the above phrase correspond to actual inner loop iteration in c code ? If so, is the number 6 in the above example, to be used in computing "expected run time" ?
Thank you in advance for your help.
Andrey
Relevant part of the .asm file:
$C$DW$L$_conv$6$E:
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 78
;* Loop opening brace source line : 78
;* Loop closing brace source line : 84
;* Loop Unroll Multiple : 4x
;* Known Minimum Trip Count : 4
;* Known Max Trip Count Factor : 4
;* Loop Carried Dependency Bound(^) : 1
;* Unpartitioned Resource Bound : 1
;* Partitioned Resource Bound(*) : 2
;* Resource Partition:
;* A-side B-side
;* .L units 0 0
;* .S units 0 0
;* .D units 1 1
;* .M units 1 1
;* .X cross paths 1 1
;* .T address paths 1 2*
;* Long read paths 0 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 1 1 (.L or .S or .D unit)
;* Bound(.L .S .LS) 0 0
;* Bound(.L .S .D .LS .LSD) 1 1
;*
;* Searching for software pipeline schedule at ...
;* ii = 2 Schedule found with 6 iterations in parallel
;*
;* Register Usage Table:
;* +-----------------------------------------------------------------+
;* |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
;* |00000000001111111111222222222233|00000000001111111111222222222233|
;* |01234567890123456789012345678901|01234567890123456789012345678901|
;* |--------------------------------+--------------------------------|
;* 0: | ***** | ***** |
;* 1: | ** | ** ** |
;* +-----------------------------------------------------------------+
;*
;* Done
;*
;* Loop will be splooped
;* Collapsed epilog stages : 0
;* Collapsed prolog stages : 0
;* Minimum required memory pad : 0 bytes
;*
;* Minimum safe trip count : 1 (after unrolling)
;* Min. prof. trip count (est.) : 2 (after unrolling)
;*
;* Mem bank conflicts/iter(est.) : { min 0.000, est 0.000, max 0.000 }
;* Mem bank perf. penalty (est.) : 0.0%
;*
;*
;* Total cycles (est.) : 10 + trip_cnt * 2
;*----------------------------------------------------------------------------*
;* SINGLE SCHEDULED ITERATION
;*
;* $C$C35:
;* 0 LDDW .D2T2 *B7++,B5:B4 ; |78| ^
;* 1 LDNDW .D1T1 *A6++(8),A5:A4 ; |78| ^
;* 2 NOP 4
;* 6 DOTP2 .M2X B4,A4,B6 ; |78| ^
;* || DOTP2 .M1X B5,A5,A3 ; |78| ^
;* 7 NOP 3
;* 10 ADD .L2 B6,B8,B8 ; |78| ^
;* || ADD .L1 A3,A7,A7 ; |78| ^
;* || SPBR $C$C35
;* 11 NOP 1
;* 12 ; BRANCHCC OCCURS {$C$C35} ; |78|
;*----------------------------------------------------------------------------*
$C$L5: ; PIPED LOOP PROLOG
; EXCLUSIVE CPU CYCLES: 11
SPLOOPD 2 ;12 ; (P)
|| MVC .S2 B4,ILC
;** --------------------------------------------------------------------------*
$C$L6: ; PIPED LOOP KERNEL
$C$DW$L$_conv$8$B:
; EXCLUSIVE CPU CYCLES: 2
LDDW .D2T2 *B7++,B5:B4 ; |78| (P) <0,0> ^
LDNDW .D1T1 *A6++(8),A5:A4 ; |78| (P) <0,1> ^
NOP 4
DOTP2 .M2X B4,A4,B6 ; |78| (P) <0,6> ^
|| DOTP2 .M1X B5,A5,A3 ; |78| (P) <0,6> ^
NOP 2
SPMASK L1,L2
|| ZERO .L1 A7 ; |78|
|| ZERO .L2 B8 ; |78|
SPKERNEL 4,1
|| ADD .L2 B6,B8,B8 ; |78| <0,10> ^
|| ADD .L1 A3,A7,A7 ; |78| <0,10> ^
$C$DW$L$_conv$8$E:
;** --------------------------------------------------------------------------*
$C$L7: ; PIPED LOOP EPILOG
; EXCLUSIVE CPU CYCLES: 9
;** --------------------------------------------------------------------------*
$C$DW$L$_conv$10$B:
; EXCLUSIVE CPU CYCLES: 12
NOP 1
MV .L1X B8,A3
.dwpsn file "../conv.c",line 86,column 9,is_stmt
ADD .L1 A7,A3,A3 ; |86|
SHR .S1 A3,15,A3 ; |86|
STH .D1T1 A3,*A24++ ; |86|
.dwpsn file "../conv.c",line 70,column 15,is_stmt
SUB .L2 B0,1,B0 ; |70|
|| ADD .S2 2,B31,B31 ; |70|
[ B0] BNOP .S1 $C$L4,4 ; |70|
|| [ B0] ADD .L2 B31,B2,B4
|| [ B0] MV .S2X A25,B7
[ B0] MV .L1X B4,A6 ; Define a twin register
; BRANCHCC OCCURS {$C$L4} ; |70|
$C$DW$L$_conv$10$E:
;** --------------------------------------------------------------------------*
