We are doing optimizations we would like to know the possible configuration of L1 L2 memory for C64x+ DSP so that there will not be any conflicts when other codecs run parallel in multi channel and multi instance scenarios….
Below are the details DSP L1 L2 memory details we got to know from the TRM.
L1P – 32KB (cache)
L1D – 32KB (cache and SRAM, programmable)
L2 - 64KB (cache and SRAM, Programmable)
L2 - 32KB (SRAM)
If these L1,L2 configurations are decided we can plan for the decoder design accordingly.
Thx,
dk