Multiple targets - DM6467

Any thoughts?

djs said:

If we have a linux HOST PC with multiple DM6467 EVM installed on the PCI Bus - what level of interaction with the ARM/DSP/HDVICP can we get? 

You could boot the board and load code to it from the host as well as communicate between the board and the host using interrupts and shared memory space.

djs said:

For example - the host  is to use the DM6467 as a video/audio transcoder.  How could this work?  The TI GStreamer plugin appears to run on the ARM.  How could we send encoding jobs to the ARM from the HOST?

There is a good bit of software to still be written to do all that you are looking to do here, primarily host driver adjustments and target application code adjustments such that the host knows how to manage the transfer of video to the target and the target knows how to take that video from the host and return the transcoded stream. To start off you may want to look at dvsdk_1_40_00_21\PSP_01_03_00_070\docs\dm646x\DM646x_PCI-Slave_UserManual.pdf and DM646x_PCI-Boot_UserManual.pdf from within your DVSDK install, these documents describe the PCI support that is included with the driver package provided by TI with the EVM.

Thanks for the reply.

If we ignore PCI totally and go for a stand alone module connected over LAN what full duplex bandwidth could we expect from the built in MAC on the DM6467?

Have you seen our App Note on Throughput overview?  It has good information on thorughput not only for EMAC, but for many other peripherals; it should also help you understand the overall system bottlenecks better.

http://focus.ti.com/dsp/docs/dspsupporttechdocsc.tsp?sectionId=3&tabId=409&familyId=1506&abstractName=spraaw4a

You could get some feel for this from the benchmarks provided in the PSP  Linux Drivers Datasheet SPRS495, in the case of LSP 1.30 see section 2.3.5.2.1 of this document, which shows up to 179Mbits/sec.

Thanks for the reply and links.  179Mbits sounds ok for our needs.  Could this improve as drivers mature?

djs said:

Could this improve as drivers mature?

Potentially yes, though there are limits relative to the device's bandwidth. One thing to keep in mind is that at 179Mbps the ARM is going to be exteremely busy handling the TCP/IP stack, so at that speed you may not be able to be doing much else in the device, in other words if your system is already loaded (i.e. DDR bandwidth, ARM MIPs, etc.) than you may not achieve the maximum possible Ethernet performance.

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djs said:

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I was wondering if you had another question here or if this was just an accidental or broken post? (I want to ensure we aren't missing something)

I am assesing the DM6467 peripherals and are looking for a faster than realtime way of getting video data into the DM6467.  What bandwith can we expect from parallel asychronous TSIF faster than realtime?  The bechmarks given are for realtime tests.

For example. Is there enough bandwidth to send 1080p30 wavelet lossless faster than realtime through the TSIF, say 45fps (375Mbit/s)?

I read somewhere that TI have used the video backend on the DM6446 to gain 1.2Gbit/s connection in raw mode to a FPGA.  Can a similar approach be used on the DM6467?

djs said:

What bandwith can we expect from parallel asychronous TSIF faster than realtime?

The TSIF in parallel mode is specified at 16.7ns minimum clock cycle period which translates to just under 60MHz max bus speed, and with an 8 bit bus that means the theoretical maximum bandwidth including the protocol header overhead would be about 480Mbps. With the asynchronous mode the actual speed would also depend on the device you are communicating with and how often the wait signal ends up being asserted, I do not know of any benchmarks for this sort of situation.

djs said:

For example. Is there enough bandwidth to send 1080p30 wavelet lossless faster than realtime through the TSIF, say 45fps (375Mbit/s)?

Potentially, though I have not seen this done, and so there may be some unforeseen limitation, it also would depend on the devices you are communicating with.

djs said:

I read somewhere that TI have used the video backend on the DM6446 to gain 1.2Gbit/s connection in raw mode to a FPGA.  Can a similar approach be used on the DM6467?

This is (theoretically) possible on the DM6446 (and other DM devices) because of the wider bus coupled with a higher clock for the bus and synchronous operation, you should be able to get similar potential from the DM6467 VPIF, which can operate at 99MHz with a 16 bit wide bus however similar to the higher rate TSIF interface this has also not been tried to my knowledge.