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Can AM3517 support a high frequency interrupt?

JIAMIN
Prodigy 140 points

Other Parts Discussed in Thread: AM3517

Hello,

I am a newbie for AM3517 and Linux.

My application is a ultrasonic device. There is a FPGA to collect the data from ADC and after doing some calculation, FPGA will send MPU an interrupt to let MPU read the data from FPGA. The frequency of interrupt is about 1KHz now. And I am trying to increase the frequency to 10KHz. However the existing design is using an old PowerPC and this MPU can't support so high frequency interrupt. For PowerPC can't finish getting the data from FPGA between two interrupts. I am planning to use AM3517 to replace the existing MPU. 

My question is whether AM3517 can support a so high frequency interrupt? And as I know, I can write a EABI program or a Linux based program. Which one is better for my application?

Thanks!

 

BR
Jiamin 

  • 0
    TI__Intellectual 2655 points

    Yes with AM3517 you should be able to support high frequency. in case where you have FPGA. you can connect FPGA to General purpose Memory controller (GPMC). this is a 16 bit interface running @ 83 MHz. what is volume of data you are trying to transfer over between 2 interrupts. you can connect external FPGA interrupt to processor you can easily get 10 K inteterrupts received.

    in addition you can use DMA controller to accelerate performance & you woudl be able to offload this memory transfer activity from CPU which allows you to freeup processor to perform other tasks.

  • 0 in reply to vaibhav
    Prodigy 140 points

    Hi, vaibhav,

    Now I read about 800 unsigned long data from FPGA between two interrupts. Do you think it's OK.

    About DMA, I need to discuss with FPGA guy. I am not familiar with it. Anyway, thanks for your advice.

     

    Jiamin

  • 0 in reply to JIAMIN
    Genius 3685 points

    <quote> "@:  you can connect external FPGA interrupt to processor you can easily get 10 K inteterrupts received" </quote>

    While I agree that this is easily possible form a HW/chip point of view I'm not sure I would recommend designing a system relying on processing 10K interrupts from one source seen from an overall System/SW point of view taking an OS into consideration as well. I would much rather go for using the interrupt signal to trigger a DMA request by connection it to one of the DMAREQx lines and utilize the DMA sub-system to totally unload the transferring of data from the SW processing (assuming that you will use GMPC for reading the data from the FPGA?).

    With respect to reading 800x4bytes@10KHz. Again it's definitely possible, but you might need to spend a little time considering the over all system design, since it actually equals ~32MB/s which can easily be handled in case done correctly, but which as well easily can lay down the complete system in case done with too many memory copies, etc...

    Just my 5 cent - Good luck with the project
      Søren