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VENC clock problem of UBL in dm365 decode

Jing1
Intellectual 580 points

 

UBL Version: 1.30

ARM: 297 MHZ

DDR: 270 MHZ

 

PLL2->PLLDIV5 = 0x8007;   // POST DIV 594/8 = 74.25 ->VIDEO HD

 

Like i set above , i decode a 720x480@30fps video , but display nothing , LCD shows nothing , but PLL2->PLLDIV5 = 0x8015( POST DIV 594/22 = 27 ->VIDEO SD) displays right . Is it means that if i want to decode a SD video i have to set the  clock to 27MHZ , and 74.25MHZ is only for HD ??

If i set the ARM to 216 MHZ and DDR to 173 MHZ , the display  works right only in 27MHZ (decode a  720x480@30fps video) , what is the highest clock i can set ???

Regards,

Katee

  • 0
    TI__Genius 9490 points

    Katee,

    Here are the answers to your questions.

    q1:Is it means that if i want to decode a SD video i have to set the  clock to 27MHZ , and 74.25MHZ is only for HD ??

    a1: yes.

    q2: If i set the ARM to 216 MHZ and DDR to 173 MHZ , the display  works right only in 27MHZ (decode a  720x480@30fps video) , what is the highest clock i can set ???

    a2: If you have purchased the DM365-216 part the max clk supported for the VENC is 27Mhz, anything above that will be out of spec.

    regards,

    miguel

  • 0 in reply to Miguel A. Alanis
    Intellectual 580 points

    Ok, I got it .  miguel , thank u so much for your help !

    ragards,

    katee