L1, L2 cache configuration

Nara Won

Other Parts Discussed in Thread: DM3730, OMAP3530

Hi Experts,

I have following question from my customer. Please, let me have your answers for the questions.

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We are doing optimizations we would like to know the possible configuration of L1 L2 memory for C64x+ DSP so that there will not be any conflicts when other codecs run parallel in multi channel and multi instance scenarios….

Below are the details DSP L1 L2 memory details we got to know from the TRM.

L1P – 32KB (cache)

L1D – 32KB (cache and SRAM, programmable)

L2 - 64KB (cache and SRAM, Programmable)

L2 - 32KB (SRAM)

If these L1,L2 configurations are decided we can plan for the decoder design accordingly.

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Nara

over 14 years ago

0 nmin Wu over 14 years ago

TI__Intellectual 910 points

I do not know which DSP you are using since different DSP may have different L2 size. For L1D and L2, you can configure them as all SRAM or all Cache or Partial Cache/Partial SRAM. For example for total 64KB L2, you can configure it as 32KB SRAM + 32 KB cache or 64KSRAM (0 Cache) or 64K cache (0 SRAM).

regards,

ywu

0 Nara Won over 14 years ago in reply to nmin Wu

TI__Intellectual 1605 points

Thank you for the reply.

DM3730 is being used.

DM3730 has C64+ core as like OMAP3530.

Nara

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L1, L2 cache configuration