• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 98 subscribers
  • Views 764 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM5728: VIP subsystem priorities

Nomo
Guru 16800 points

Part Number: AM5728

Hello,

In 9.4.8.5 of TRM for AM5728, the following is described.
"Priority escalation mechanism implemented within VIP subsystem is based on overflow threshold and FIFO margin."
My customers want to know the priority from VIP (VPDMA) to DDR and they have the following questions.

1.What is the priority escalation mechanism?
  Is the priority of VPDMA changed dynamically by the FIFO margin?

2.In case the priority is the same for each VPDMA, could you tell me the priority of the access from VPDMA to DDR?+

3.Could you let me know the priority of accessing from VIP Slice to L3_MAIN through VPDMA?

4.Could you tell me the detail specification of switching port A and B connecting VIP Slice0/1?

Best Regards,
Nomo

  • 0
    TI__Guru**** 393215 points
    The factory team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Mastermind 22946 points

    Hi Nomo,

    What issue are you facing exactly? In case your system is having high DDR traffic and you are seeing camera capture underflow issue, check section 15.2.3.5.3.3 PEG Description of TRM document to set the DMM Peg priority register. Refer to Table 14-10. ConnID Values for the connId value of VIP VPDMA. 

  • 0 in reply to Manisha Agrawal
    Guru 16800 points
    Hello manisha-san,

    Thank you for your reply.
    My customers want to estimate how many input can be connected to the VIP modules.
    They are concerned about the worse throughput by the large connection.
    If throughput will be worse, they will consider using external multiplexers.

    Best Regards,
    Nomo
  • 0 in reply to Nomo
    TI__Mastermind 22946 points

    AM5728 has 10 video capture ports which can be clocked at 165 MHz. Below table shows the port IDs with bus width. The number of cameras you can hook on AM5728 device depends upon the resolution, frame rate and pin-mix availability. For example, it can theoretically support upto 6x1080p60 16 bit camera capture, provided  pin-mux availability. It can support more number of cameras for lower resolution/fps.

    Port # VIN ID Port bus width
    1 VIN1 A 24/16/8 bit
    2 VIN1 B 8 bit
    3 VIN2 A 24/16/8 bit
    4 VIN2 B 8 bit
    5 VIN3 A 24/16/8 bit
    6 VIN3 B 8 bit
    7 VIN4 A 24/16/8 bit
    8 VIN4 B 8 bit
    9 VIN5 A 16 bit
    10 VIN6 A 16 bit

    Regarding throughput, it depends upon system DDR BW. AM5728 can handle around upto 4.5 GBytes/sec of DDR traffic. If the system DDR traffic is at the verge of DDR BW limit, then you need to play with DMM peg priority register to bump up the priority of different masters who are sensitive to real time access to DDR data.

  • 0 in reply to Manisha Agrawal
    Guru 16800 points
    Hello manisha-san,

    Thank you for your reply.
    I will estimate the throughput based on your information.

    Best Regards,
    Nomo